mirror of
https://github.com/RPCS3/llvm.git
synced 2026-08-28 05:10:05 -04:00
Matt Arsenault
e536396218
------------------------------------------------------------------------ r292982 | arsenm | 2017-01-24 14:02:15 -0800 (Tue, 24 Jan 2017) | 8 lines Enable FeatureFlatForGlobal on Volcanic Islands This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@293326 91177308-0d34-0410-b5e6-96231b3b80d8
317 lines
10 KiB
LLVM
317 lines
10 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; FIXME: Merge into imm.ll
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; GCN-LABEL: {{^}}store_inline_imm_neg_0.0_i16:
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x8000{{$}}
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; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff8000{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_neg_0.0_i16(i16 addrspace(1)* %out) {
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store volatile i16 -32768, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_0.0_f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_0.0_f16(half addrspace(1)* %out) {
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store half 0.0, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_imm_neg_0.0_f16:
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x8000{{$}}
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; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff8000{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_imm_neg_0.0_f16(half addrspace(1)* %out) {
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store half -0.0, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_0.5_f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3800{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_0.5_f16(half addrspace(1)* %out) {
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store half 0.5, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_m_0.5_f16:
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xb800{{$}}
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; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffb800{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_m_0.5_f16(half addrspace(1)* %out) {
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store half -0.5, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_1.0_f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3c00{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_1.0_f16(half addrspace(1)* %out) {
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store half 1.0, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_m_1.0_f16:
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xbc00{{$}}
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; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffbc00{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_m_1.0_f16(half addrspace(1)* %out) {
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store half -1.0, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_2.0_f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x4000{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_2.0_f16(half addrspace(1)* %out) {
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store half 2.0, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_m_2.0_f16:
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xc000{{$}}
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; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffc000{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_m_2.0_f16(half addrspace(1)* %out) {
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store half -2.0, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_4.0_f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x4400{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_4.0_f16(half addrspace(1)* %out) {
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store half 4.0, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_m_4.0_f16:
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xc400{{$}}
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; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffc400{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_m_4.0_f16(half addrspace(1)* %out) {
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store half -4.0, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_inv_2pi_f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3118{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_inv_2pi_f16(half addrspace(1)* %out) {
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store half 0xH3118, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_m_inv_2pi_f16:
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xb118{{$}}
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; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffb118{{$}}
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; GCN: buffer_store_short [[REG]]
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define void @store_inline_imm_m_inv_2pi_f16(half addrspace(1)* %out) {
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store half 0xHB118, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_literal_imm_f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x6c00
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; GCN: buffer_store_short [[REG]]
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define void @store_literal_imm_f16(half addrspace(1)* %out) {
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store half 4096.0, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_0.0_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_0.0_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 0.0
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_0.5_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_0.5_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 0.5
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_0.5_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_neg_0.5_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, -0.5
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_1.0_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_1.0_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 1.0
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_1.0_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_neg_1.0_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, -1.0
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_2.0_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_2.0_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 2.0
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_2.0_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_neg_2.0_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, -2.0
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_4.0_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_4.0_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 4.0
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_4.0_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_neg_4.0_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, -4.0
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}commute_add_inline_imm_0.5_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]
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; VI: buffer_store_short [[REG]]
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define void @commute_add_inline_imm_0.5_f16(half addrspace(1)* %out, half addrspace(1)* %in) {
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%x = load half, half addrspace(1)* %in
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%y = fadd half %x, 0.5
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}commute_add_literal_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 0x6400, [[VAL]]
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; VI: buffer_store_short [[REG]]
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define void @commute_add_literal_f16(half addrspace(1)* %out, half addrspace(1)* %in) {
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%x = load half, half addrspace(1)* %in
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%y = fadd half %x, 1024.0
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_1_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_1_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 0xH0001
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_2_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 2, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_2_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 0xH0002
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_16_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 16, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_16_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 0xH0010
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_1_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], -1, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_neg_1_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 0xHFFFF
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_2_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], -2, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_neg_2_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 0xHFFFE
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_16_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], -16, [[VAL]]{{$}}
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_neg_16_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 0xHFFF0
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_63_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 63, [[VAL]]
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_63_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 0xH003F
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store half %y, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_64_f16:
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; VI: v_add_f16_e32 [[REG:v[0-9]+]], 64, [[VAL]]
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; VI: buffer_store_short [[REG]]
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define void @add_inline_imm_64_f16(half addrspace(1)* %out, half %x) {
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%y = fadd half %x, 0xH0040
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store half %y, half addrspace(1)* %out
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ret void
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}
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