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https://github.com/RPCS3/llvm.git
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Matt Arsenault
e536396218
------------------------------------------------------------------------ r292982 | arsenm | 2017-01-24 14:02:15 -0800 (Tue, 24 Jan 2017) | 8 lines Enable FeatureFlatForGlobal on Volcanic Islands This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@293326 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
2.5 KiB
LLVM
57 lines
2.5 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare float @llvm.fabs.f32(float) nounwind readnone
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declare float @llvm.AMDGPU.clamp.f32(float, float, float) nounwind readnone
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; FUNC-LABEL: {{^}}clamp_0_1_f32:
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; SI: s_load_dword [[ARG:s[0-9]+]],
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; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], [[ARG]], 0 clamp{{$}}
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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; EG: MOV_SAT
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define void @clamp_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
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%clamp = call float @llvm.AMDGPU.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone
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store float %clamp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}clamp_fabs_0_1_f32:
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; SI: s_load_dword [[ARG:s[0-9]+]],
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; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], |[[ARG]]|, 0 clamp{{$}}
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @clamp_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
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%src.fabs = call float @llvm.fabs.f32(float %src) nounwind readnone
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%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fabs, float 0.0, float 1.0) nounwind readnone
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store float %clamp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}clamp_fneg_0_1_f32:
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; SI: s_load_dword [[ARG:s[0-9]+]],
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; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], -[[ARG]], 0 clamp{{$}}
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @clamp_fneg_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
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%src.fneg = fsub float -0.0, %src
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%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg, float 0.0, float 1.0) nounwind readnone
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store float %clamp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}clamp_fneg_fabs_0_1_f32:
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; SI: s_load_dword [[ARG:s[0-9]+]],
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; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], -|[[ARG]]|, 0 clamp{{$}}
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @clamp_fneg_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
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%src.fabs = call float @llvm.fabs.f32(float %src) nounwind readnone
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%src.fneg.fabs = fsub float -0.0, %src.fabs
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%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg.fabs, float 0.0, float 1.0) nounwind readnone
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store float %clamp, float addrspace(1)* %out, align 4
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ret void
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}
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