mirror of
https://github.com/RPCS3/llvm.git
synced 2026-08-28 05:10:05 -04:00
Matt Arsenault
e536396218
------------------------------------------------------------------------ r292982 | arsenm | 2017-01-24 14:02:15 -0800 (Tue, 24 Jan 2017) | 8 lines Enable FeatureFlatForGlobal on Volcanic Islands This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@293326 91177308-0d34-0410-b5e6-96231b3b80d8
166 lines
8.1 KiB
LLVM
166 lines
8.1 KiB
LLVM
; RUN: llc < %s -march=amdgcn -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=SIVI %s
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; RUN: llc < %s -march=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=CI --check-prefix=GCN %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=SIVI %s
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; SMRD load with an immediate offset.
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; GCN-LABEL: {{^}}smrd0:
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; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
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define void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 1
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%1 = load i32, i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with the largest possible immediate offset.
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; GCN-LABEL: {{^}}smrd1:
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; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
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define void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 255
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%1 = load i32, i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate.
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; GCN-LABEL: {{^}}smrd2:
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; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
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; GCN: s_endpgm
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define void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 256
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%1 = load i32, i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with a 64-bit offset
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; GCN-LABEL: {{^}}smrd3:
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; FIXME: There are too many copies here because we don't fold immediates
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; through REG_SEQUENCE
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; SI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b
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; TODO: Add VI checks
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; GCN: s_endpgm
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define void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 4294967296 ; 2 ^ 32
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%1 = load i32, i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with the largest possible immediate offset on VI
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; GCN-LABEL: {{^}}smrd4:
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; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
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define void @smrd4(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 262143
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%1 = load i32, i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate on VI
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; GCN-LABEL: {{^}}smrd5:
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; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
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; SIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
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; GCN: s_endpgm
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define void @smrd5(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 262144
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%1 = load i32, i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load using the load.const intrinsic with an immediate offset
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; GCN-LABEL: {{^}}smrd_load_const0:
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; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
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; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10
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define amdgpu_ps void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) {
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main_body:
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%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
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ret void
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}
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; SMRD load using the load.const intrinsic with the largest possible immediate
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; offset.
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; GCN-LABEL: {{^}}smrd_load_const1:
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; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
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; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
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define amdgpu_ps void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) {
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main_body:
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%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1020)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
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ret void
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}
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; SMRD load using the load.const intrinsic with an offset greater than the
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; largets possible immediate.
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; immediate offset.
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; GCN-LABEL: {{^}}smrd_load_const2:
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; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
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; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
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; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
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; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
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define amdgpu_ps void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) {
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main_body:
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%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1024)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
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ret void
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}
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; SMRD load with the largest possible immediate offset on VI
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; GCN-LABEL: {{^}}smrd_load_const3:
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; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
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; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
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; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
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define amdgpu_ps void @smrd_load_const3(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) {
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main_body:
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%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1048572)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate on VI
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; GCN-LABEL: {{^}}smrd_load_const4:
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; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
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; SIVI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
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; GCN: s_endpgm
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define amdgpu_ps void @smrd_load_const4(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) {
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main_body:
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%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1048576)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.load.const(<16 x i8>, i32) #0
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { nounwind readnone }
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