mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-22 11:45:31 -04:00
Tom Stellard
b4989f049a
------------------------------------------------------------------------ r260658 | Matthew.Arsenault | 2016-02-11 22:31:30 -0800 (Thu, 11 Feb 2016) | 12 lines AMDGPU: Set flat_scratch from flat_scratch_init reg This was hardcoded to the static private size, but this would be missing the offset and additional size for someday when we have dynamic sizing. Also stops always initializing flat_scratch even when unused. In the future we should stop emitting this unless flat instructions are used to access private memory. For example this will initialize it almost always on VI because flat is used for global access. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271684 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
2.2 KiB
LLVM
64 lines
2.2 KiB
LLVM
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj | llvm-readobj -symbols -s -sd | FileCheck --check-prefix=ELF %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF
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; The SHT_NOTE section contains the output from the .hsa_code_object_*
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; directives.
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; ELF: Section {
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; ELF: Name: .hsatext
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; ELF: Type: SHT_PROGBITS (0x1)
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; ELF: Flags [ (0xC00007)
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; ELF: SHF_ALLOC (0x2)
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; ELF: SHF_AMDGPU_HSA_AGENT (0x800000)
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; ELF: SHF_AMDGPU_HSA_CODE (0x400000)
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; ELF: SHF_EXECINSTR (0x4)
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; ELF: SHF_WRITE (0x1)
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; ELF: }
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; ELF: SHT_NOTE
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; ELF: 0000: 04000000 08000000 01000000 414D4400
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; ELF: 0010: 01000000 00000000 04000000 1B000000
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; ELF: 0020: 03000000 414D4400 04000700 07000000
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; ELF: 0030: 00000000 00000000 414D4400 414D4447
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; ELF: 0040: 50550000
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; ELF: Symbol {
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; ELF: Name: simple
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; ELF: Size: 288
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; ELF: Type: AMDGPU_HSA_KERNEL (0xA)
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; ELF: }
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; HSA: .hsa_code_object_version 1,0
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; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
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; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
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; HSA: .hsatext
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; HSA: .amdgpu_hsa_kernel simple
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; HSA: {{^}}simple:
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; HSA: .amd_kernel_code_t
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: .end_amd_kernel_code_t
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; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
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; Make sure we are setting the ATC bit:
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; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000
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; On VI+ we also need to set MTYPE = 2
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; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
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; Make sure we generate flat store for HSA
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; HSA: flat_store_dword v{{[0-9]+}}
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; HSA: .Lfunc_end0:
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; HSA: .size simple, .Lfunc_end0-simple
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define void @simple(i32 addrspace(1)* %out) {
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entry:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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