Alex Bradbury d25fc4439d [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero ...

c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C.
This patch adds uimmlog2xlennonzero to reflect this constraint as well as
tests.

Differential Revision: https://reviews.llvm.org/D41216

Patch by Shiva Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320799 91177308-0d34-0410-b5e6-96231b3b80d8

2017-12-15 10:20:51 +00:00

..

CMakeLists.txt

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LLVMBuild.txt

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RISCVAsmParser.cpp

[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero

2017-12-15 10:20:51 +00:00