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Francis Visoiu Mistrih
7384652668
As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319427 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
920 B
YAML
31 lines
920 B
YAML
# RUN: llc -march=amdgcn -run-pass liveintervals -verify-machineinstrs -o /dev/null -debug-only=regalloc %s 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# We currently maintain a main liveness range which operates like a superset of
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# all subregister liveranges. We may need to create additional SSA values at
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# merge point in this main liverange even though none of the subregister
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# liveranges needed it.
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#
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# Should see three distinct value numbers:
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# CHECK: %0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}}
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--- |
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define amdgpu_kernel void @test0() { ret void }
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...
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---
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name: test0
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registers:
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- { id: 0, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def undef %0.sub0
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S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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S_BRANCH %bb.2
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bb.1:
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S_NOP 0, implicit-def %0.sub1
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S_NOP 0, implicit %0.sub1
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S_BRANCH %bb.2
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bb.2:
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S_NOP 0, implicit %0.sub0
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...
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