Files
llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
Geoff Berry 7946cf61b7 [AArch64] Fix bug in store of vector 0 DAGCombine.
Summary:
Avoid using XZR/WZR directly as operands to split stores of zero
vectors.  Doing so can lead to the XZR/WZR being used by an instruction
that doesn't allow it (e.g. add).

Fixes bug 34674.

Reviewers: t.p.northover, efriedma, MatzeB

Subscribers: aemerson, rengolin, javed.absar, mcrosier, eraman, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D38146

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313916 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-21 21:10:06 +00:00

28 lines
841 B
LLVM

; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define void @t1(i8* nocapture %c) nounwind optsize {
entry:
; CHECK-LABEL: t1:
; CHECK: str wzr, [x0, #8]
; CHECK: str xzr, [x0]
call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false)
ret void
}
define void @t2() nounwind ssp {
entry:
; CHECK-LABEL: t2:
; CHECK: stp xzr, xzr, [sp, #16]
; CHECK: strh wzr, [sp, #32]
; CHECK: str xzr, [sp, #8]
%buf = alloca [26 x i8], align 1
%0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0
call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false)
call void @something(i8* %0) nounwind
ret void
}
declare void @something(i8*) nounwind
declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind