mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-22 03:35:35 -04:00
Nicolai Haehnle
da47d9d5d0
The hardware will only forward EXEC_LO; the high 32 bits will be zero. Additionally, inline constants do not work. At least, v_addc_u32_e64 v0, vcc, v0, v1, -1 which could conceivably be used to combine (v0 + v1 + 1) into a single instruction, acts as if all carry-in bits are zero. The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine s_mov_b64 s[0:1], exec v_cndmask_b32_e64 v0, v1, v2, s[0:1] into v_mov_b32 v0, v3 but it's not particularly high priority. Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314522 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
2.4 KiB
YAML
98 lines
2.4 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: subbrev{{$}}
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# GCN: V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec
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---
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name: subbrev
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
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%4, %5 = V_SUBBREV_U32_e64 0, %0, %3, implicit %exec
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...
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# GCN-LABEL: name: subb{{$}}
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# GCN: V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec
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---
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name: subb
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
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%4, %5 = V_SUBB_U32_e64 %0, 0, %3, implicit %exec
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...
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# GCN-LABEL: name: addc{{$}}
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# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
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---
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name: addc
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
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%4, %5 = V_ADDC_U32_e64 0, %0, %3, implicit %exec
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...
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# GCN-LABEL: name: addc2{{$}}
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# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
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---
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name: addc2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
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%4, %5 = V_ADDC_U32_e64 %0, 0, %3, implicit %exec
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...
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