mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-22 03:35:35 -04:00
Matt Arsenault
2e48864110
Try to avoid mutually exclusive features. Don't use a real default GPU, and use a fake "generic". The goal is to make it easier to see which set of features are incompatible between feature strings. Most of the test changes are due to random scheduling changes from not having a default fullspeed model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310258 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
2.8 KiB
LLVM
96 lines
2.8 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}uitofp_i16_to_f16
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; GCN: buffer_load_ushort v[[A_I16:[0-9]+]]
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; SI: v_cvt_f32_u32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]
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; VI: v_cvt_f32_i32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]
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; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uitofp_i16_to_f16(
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half addrspace(1)* %r,
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i16 addrspace(1)* %a) {
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entry:
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%a.val = load i16, i16 addrspace(1)* %a
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%r.val = uitofp i16 %a.val to half
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}uitofp_i32_to_f16
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; GCN: buffer_load_dword v[[A_I32:[0-9]+]]
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; GCN: v_cvt_f32_u32_e32 v[[A_I16:[0-9]+]], v[[A_I32]]
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; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_I16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uitofp_i32_to_f16(
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half addrspace(1)* %r,
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i32 addrspace(1)* %a) {
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entry:
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%a.val = load i32, i32 addrspace(1)* %a
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%r.val = uitofp i32 %a.val to half
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; f16 = uitofp i64 is in uint_to_fp.i64.ll
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; GCN-LABEL: {{^}}uitofp_v2i16_to_v2f16
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; GCN: buffer_load_dword
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; SI: v_cvt_f32_u32_e32
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; SI: v_cvt_f32_u32_e32
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; SI: v_cvt_f16_f32_e32
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; SI: v_cvt_f16_f32_e32
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; SI-DAG: v_lshlrev_b32_e32
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; SI: v_or_b32_e32
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; VI-DAG: v_cvt_f16_f32_e32
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; VI-DAG: v_cvt_f32_i32_sdwa
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; VI-DAG: v_cvt_f32_i32_sdwa
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; VI-DAG: v_cvt_f16_f32_sdwa
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; VI: v_or_b32_e32
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; GCN: buffer_store_dword
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; GCN: s_endpgm
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define amdgpu_kernel void @uitofp_v2i16_to_v2f16(
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<2 x half> addrspace(1)* %r,
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<2 x i16> addrspace(1)* %a) {
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entry:
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%a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
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%r.val = uitofp <2 x i16> %a.val to <2 x half>
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}uitofp_v2i32_to_v2f16
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; GCN: buffer_load_dwordx2
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; SI: v_cvt_f32_u32_e32
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; SI: v_cvt_f32_u32_e32
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; SI: v_cvt_f16_f32_e32
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; SI: v_cvt_f16_f32_e32
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; SI-DAG: v_lshlrev_b32_e32
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; SI: v_or_b32_e32
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; VI-DAG: v_cvt_f32_u32_e32
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; VI-DAG: v_cvt_f32_u32_e32
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; VI-DAG: v_cvt_f16_f32_e32
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; VI-DAG: v_cvt_f16_f32_sdwa
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; VI: v_or_b32_e32
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; GCN: buffer_store_dword
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; GCN: s_endpgm
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define amdgpu_kernel void @uitofp_v2i32_to_v2f16(
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<2 x half> addrspace(1)* %r,
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<2 x i32> addrspace(1)* %a) {
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entry:
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%a.val = load <2 x i32>, <2 x i32> addrspace(1)* %a
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%r.val = uitofp <2 x i32> %a.val to <2 x half>
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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; f16 = uitofp i64 is in uint_to_fp.i64.ll
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