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https://github.com/RPCS3/llvm.git
synced 2026-07-25 20:55:54 -04:00
Eli Friedman
617c526c5c
In ARMPreAllocLoadStoreOpt::RescheduleOps, LastOp should be the last operation which we want to merge. If we break out of the loop because an operation has the wrong offset, we shouldn't use that operation as LastOp. This patch fixes some cases where we would move stores to the wrong insert point. Re-commit with a fix to increment NumMove in the right place. Differential Revision: https://reviews.llvm.org/D30124 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296815 91177308-0d34-0410-b5e6-96231b3b80d8
106 lines
3.0 KiB
YAML
106 lines
3.0 KiB
YAML
# RUN: llc -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s
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--- |
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target triple = "thumbv7---eabi"
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define void @a(i32* nocapture %x, i32 %y, i32 %z) {
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entry:
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ret void
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}
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define void @b(i32* nocapture %x, i32 %y, i32 %z) {
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entry:
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ret void
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}
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...
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---
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# CHECK-LABEL: name: a
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name: a
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alignment: 1
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tracksRegLiveness: true
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liveins:
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- { reg: '%r0', virtual-reg: '%0' }
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- { reg: '%r1', virtual-reg: '%1' }
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- { reg: '%r2', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: %r0, %r1, %r2
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%2 : rgpr = COPY %r2
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%1 : rgpr = COPY %r1
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%0 : gpr = COPY %r0
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%3 : rgpr = t2MUL %2, %2, 14, _
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%4 : rgpr = t2MUL %1, %1, 14, _
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%5 : rgpr = t2MOVi32imm -858993459
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%6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, _
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%8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, _
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t2STRi12 %1, %0, 0, 14, _ :: (store 4)
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%10 : rgpr = t2LSLri %2, 1, 14, _, _
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t2STRi12 killed %10, %0, 4, 14, _ :: (store 4)
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; Make sure we move the paired stores next to each other, and
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; insert them in an appropriate location.
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; CHECK: t2STRi12 %1,
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; CHECK-NEXT: t2STRi12 killed %10,
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; CHECK-NEXT: t2MOVi
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; CHECK-NEXT: t2ADDrs
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%11 : rgpr = t2MOVi 55, 14, _, _
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%12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, _, _
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t2STRi12 killed %12, %0, 16, 14, _ :: (store 4)
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%13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, _, _
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t2STRi12 killed %13, %0, 20, 14, _ :: (store 4)
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; Make sure we move the paired stores next to each other.
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; CHECK: t2STRi12 killed %12,
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; CHECK-NEXT: t2STRi12 killed %13,
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tBX_RET 14, _
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---
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# CHECK-LABEL: name: b
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name: b
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alignment: 1
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tracksRegLiveness: true
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liveins:
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- { reg: '%r0', virtual-reg: '%0' }
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- { reg: '%r1', virtual-reg: '%1' }
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- { reg: '%r2', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: %r0, %r1, %r2
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%2 : rgpr = COPY %r2
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%1 : rgpr = COPY %r1
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%0 : gpr = COPY %r0
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t2STRi12 %1, %0, 0, 14, _ :: (store 4)
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%10 : rgpr = t2LSLri %2, 1, 14, _, _
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t2STRi12 killed %10, %0, 4, 14, _ :: (store 4)
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%3 : rgpr = t2MUL %2, %2, 14, _
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t2STRi12 %3, %0, 8, 14, _ :: (store 4)
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; Make sure we move the paired stores next to each other, and
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; insert them in an appropriate location.
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; CHECK: t2STRi12 {{.*}}, 0
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; CHECK-NEXT: t2STRi12 {{.*}}, 4
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; CHECK-NEXT: t2STRi12 {{.*}}, 8
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; CHECK-NEXT: t2MUL
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; CHECK-NEXT: t2MOVi32imm
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%4 : rgpr = t2MUL %1, %1, 14, _
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%5 : rgpr = t2MOVi32imm -858993459
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%6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, _
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%8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, _
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%10 : rgpr = t2LSLri %2, 1, 14, _, _
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%11 : rgpr = t2MOVi 55, 14, _, _
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%12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, _, _
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t2STRi12 killed %12, %0, 16, 14, _ :: (store 4)
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%13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, _, _
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t2STRi12 killed %13, %0, 20, 14, _ :: (store 4)
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; Make sure we move the paired stores next to each other.
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; CHECK: t2STRi12 {{.*}}, 16
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; CHECK-NEXT: t2STRi12 {{.*}}, 20
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tBX_RET 14, _
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...
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