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https://github.com/RPCS3/llvm.git
synced 2026-07-22 11:45:31 -04:00
Dylan McKay
d2c33c4ecb
Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287162 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
949 B
LLVM
38 lines
949 B
LLVM
; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
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; CHECK-LABEL: atomic_store8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
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; CHECK-NEXT: out 63, r0
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define void @atomic_store8(i8* %foo) {
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store atomic i8 1, i8* %foo unordered, align 1
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ret void
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}
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; CHECK-LABEL: atomic_store16
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
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; CHECK-NEXT: std [[RD]]+1, [[RR:r[0-9]+]]
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; CHECK-NEXT: out 63, r0
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define void @atomic_store16(i16* %foo) {
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store atomic i16 1, i16* %foo unordered, align 2
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ret void
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}
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; CHECK-LABEL: atomic_store32
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; CHECK: call __sync_lock_test_and_set_4
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define void @atomic_store32(i32* %foo) {
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store atomic i32 1, i32* %foo unordered, align 4
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ret void
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}
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; CHECK-LABEL: atomic_store64
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; CHECK: call __sync_lock_test_and_set_8
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define void @atomic_store64(i64* %foo) {
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store atomic i64 1, i64* %foo unordered, align 8
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ret void
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}
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