mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-24 12:15:51 -04:00
Zhan Jun Liau
ff74d2352e
Summary:
Created a pattern to match 64-bit mode (and (xor x, -1), y)
to a shorter sequence of instructions.
Before the change, the canonical form is translated to:
xihf %r3, 4294967295
xilf %r3, 4294967295
ngr %r2, %r3
After the change, the canonical form is translated to:
ngr %r3, %r2
xgr %r2, %r3
Reviewers: zhanjunl, uweigand
Subscribers: llvm-commits
Author: assem
Committing on behalf of Assem.
Differential Revision: http://reviews.llvm.org/D21693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273887 91177308-0d34-0410-b5e6-96231b3b80d8
15 lines
312 B
LLVM
15 lines
312 B
LLVM
; Testing peephole for generating shorter code for (and (xor b, -1), a)
|
|
;
|
|
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
|
|
|
define i64 @f1(i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f1:
|
|
; CHECK: ngr %r3, %r2
|
|
; CHECK: xgr %r2, %r3
|
|
; CHECK: br %r14
|
|
%neg = xor i64 %b, -1
|
|
%and = and i64 %neg, %a
|
|
ret i64 %and
|
|
}
|
|
|