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Craig Topper
2f8aabcbb0
If we allow the OR to be narrowed then the upper bits really are zero and we can't tell if the zeroing movl was removed on purpose. While here regenerate the test with update_llc_test_checks.py git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312995 91177308-0d34-0410-b5e6-96231b3b80d8
21 lines
614 B
LLVM
21 lines
614 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O2 -mtriple=x86_64-unknown-unknown | FileCheck %s
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; Checks that a zeroing mov is inserted for the trunc/zext pair even when
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; the source of the zext is an AssertSext node
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; PR20494
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define i64 @main(i64 %a) {
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; CHECK-LABEL: main:
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; CHECK: # BB#0:
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; CHECK-NEXT: orq $-2, %rdi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%or = or i64 %a, -2
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%trunc = trunc i64 %or to i32
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br label %l
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l:
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%ext = zext i32 %trunc to i64
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trunc i64 %or to i32 ; to keep the or from being narrowed
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ret i64 %ext
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}
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