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https://github.com/RPCS3/llvm.git
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Matthias Braun
3a6f6d93bf
`llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309774 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.7 KiB
LLVM
46 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 | FileCheck %s
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; rdar://11897677
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;CHECK-LABEL: intrin_pmov:
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;CHECK: pmovzxbw (%{{.*}}), %xmm0
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;CHECK-NEXT: movdqu
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;CHECK-NEXT: ret
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define void @intrin_pmov(i16* noalias %dest, i8* noalias %src) nounwind uwtable ssp {
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%1 = bitcast i8* %src to <2 x i64>*
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%2 = load <2 x i64>, <2 x i64>* %1, align 16
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%3 = bitcast <2 x i64> %2 to <16 x i8>
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%4 = tail call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %3) nounwind
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%5 = bitcast i16* %dest to i8*
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%6 = bitcast <8 x i16> %4 to <16 x i8>
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tail call void @llvm.x86.sse2.storeu.dq(i8* %5, <16 x i8> %6) nounwind
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ret void
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}
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declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>) nounwind readnone
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declare void @llvm.x86.sse2.storeu.dq(i8*, <16 x i8>) nounwind
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; rdar://15245794
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define <4 x i32> @foo0(double %v.coerce) nounwind ssp {
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; CHECK-LABEL: foo0
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; CHECK: pmovzxwd %xmm0, %xmm0
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; CHECK-NEXT: ret
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%tmp = bitcast double %v.coerce to <4 x i16>
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%tmp1 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%tmp2 = tail call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp1) nounwind
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ret <4 x i32> %tmp2
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}
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define <8 x i16> @foo1(double %v.coerce) nounwind ssp {
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; CHECK-LABEL: foo1
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; CHECK: pmovzxbw %xmm0, %xmm0
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; CHECK-NEXT: ret
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%tmp = bitcast double %v.coerce to <8 x i8>
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%tmp1 = shufflevector <8 x i8> %tmp, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%tmp2 = tail call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %tmp1)
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ret <8 x i16> %tmp2
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}
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declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
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