mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-23 12:15:39 -04:00
Elad Cohen
605e60b1d2
When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311071 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
1.9 KiB
LLVM
53 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mattr=+avx512f | FileCheck %s
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; RUN: llc < %s -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @test() local_unnamed_addr {
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; CHECK-LABEL: test:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,3]
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; CHECK-NEXT: vpextrq $1, %xmm0, %rax
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; CHECK-NEXT: vmovq %xmm0, %rcx
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; CHECK-NEXT: negq %rdx
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; CHECK-NEXT: fld1
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; CHECK-NEXT: fldz
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; CHECK-NEXT: fld %st(0)
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; CHECK-NEXT: fcmove %st(2), %st(0)
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; CHECK-NEXT: cmpq %rax, %rcx
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; CHECK-NEXT: fld %st(1)
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; CHECK-NEXT: fcmove %st(3), %st(0)
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; CHECK-NEXT: cmpq %rax, %rax
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; CHECK-NEXT: fld %st(2)
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; CHECK-NEXT: fcmove %st(4), %st(0)
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: cmpq %rax, %rax
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; CHECK-NEXT: fld %st(3)
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; CHECK-NEXT: fcmove %st(5), %st(0)
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; CHECK-NEXT: fstp %st(5)
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; CHECK-NEXT: fxch %st(2)
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; CHECK-NEXT: fadd %st(3)
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; CHECK-NEXT: fxch %st(4)
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; CHECK-NEXT: fadd %st(3)
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; CHECK-NEXT: fxch %st(2)
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; CHECK-NEXT: fadd %st(3)
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; CHECK-NEXT: fxch %st(1)
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; CHECK-NEXT: faddp %st(3)
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; CHECK-NEXT: fxch %st(3)
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; CHECK-NEXT: fstpt (%rax)
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; CHECK-NEXT: fxch %st(1)
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; CHECK-NEXT: fstpt (%rax)
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; CHECK-NEXT: fxch %st(1)
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; CHECK-NEXT: fstpt (%rax)
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; CHECK-NEXT: fstpt (%rax)
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%1 = icmp eq <4 x i64> <i64 0, i64 1, i64 2, i64 3>, undef
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%2 = select <4 x i1> %1, <4 x x86_fp80> <x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000>, <4 x x86_fp80> zeroinitializer
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%3 = fadd <4 x x86_fp80> undef, %2
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%4 = shufflevector <4 x x86_fp80> %3, <4 x x86_fp80> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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store <8 x x86_fp80> %4, <8 x x86_fp80>* undef, align 16
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unreachable
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}
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