mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-23 12:15:39 -04:00
Sanjay Patel
bea559baff
This is the backend counterpart to: https://reviews.llvm.org/rL297390 https://reviews.llvm.org/rL297409 and follow-up to: https://reviews.llvm.org/rL297384 It surprised me that we need to duplicate the check in FoldConstantArithmetic and FoldConstantVectorArithmetic, but one or the other doesn't catch all of the test cases. There is an existing code comment about merging those someday. Differential Revision: https://reviews.llvm.org/D30826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297762 91177308-0d34-0410-b5e6-96231b3b80d8
200 lines
6.2 KiB
LLVM
200 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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define <8 x i16> @sdiv_vec8x16(<8 x i16> %var) {
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; SSE-LABEL: sdiv_vec8x16:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psraw $15, %xmm1
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; SSE-NEXT: psrlw $11, %xmm1
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; SSE-NEXT: paddw %xmm0, %xmm1
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; SSE-NEXT: psraw $5, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sdiv_vec8x16:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpsraw $15, %xmm0, %xmm1
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; AVX-NEXT: vpsrlw $11, %xmm1, %xmm1
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; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsraw $5, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
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ret <8 x i16> %0
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}
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define <8 x i16> @sdiv_vec8x16_minsize(<8 x i16> %var) minsize {
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; SSE-LABEL: sdiv_vec8x16_minsize:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psraw $15, %xmm1
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; SSE-NEXT: psrlw $11, %xmm1
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; SSE-NEXT: paddw %xmm0, %xmm1
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; SSE-NEXT: psraw $5, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sdiv_vec8x16_minsize:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpsraw $15, %xmm0, %xmm1
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; AVX-NEXT: vpsrlw $11, %xmm1, %xmm1
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; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsraw $5, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
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ret <8 x i16> %0
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}
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define <4 x i32> @sdiv_vec4x32(<4 x i32> %var) {
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; SSE-LABEL: sdiv_vec4x32:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psrld $28, %xmm1
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: psrad $4, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sdiv_vec4x32:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX-NEXT: vpsrld $28, %xmm1, %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsrad $4, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = sdiv <4 x i32> %var, <i32 16, i32 16, i32 16, i32 16>
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ret <4 x i32> %0
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}
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define <4 x i32> @sdiv_negative(<4 x i32> %var) {
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; SSE-LABEL: sdiv_negative:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psrld $28, %xmm1
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: psrad $4, %xmm1
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; SSE-NEXT: pxor %xmm0, %xmm0
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sdiv_negative:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX-NEXT: vpsrld $28, %xmm1, %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsrad $4, %xmm0, %xmm0
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = sdiv <4 x i32> %var, <i32 -16, i32 -16, i32 -16, i32 -16>
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ret <4 x i32> %0
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}
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define <8 x i32> @sdiv8x32(<8 x i32> %var) {
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; SSE-LABEL: sdiv8x32:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: psrad $31, %xmm2
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; SSE-NEXT: psrld $26, %xmm2
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; SSE-NEXT: paddd %xmm0, %xmm2
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; SSE-NEXT: psrad $6, %xmm2
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; SSE-NEXT: movdqa %xmm1, %xmm3
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; SSE-NEXT: psrad $31, %xmm3
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; SSE-NEXT: psrld $26, %xmm3
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; SSE-NEXT: paddd %xmm1, %xmm3
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; SSE-NEXT: psrad $6, %xmm3
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: movdqa %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: sdiv8x32:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld $26, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX1-NEXT: vpsrad $6, %xmm1, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm2
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; AVX1-NEXT: vpsrld $26, %xmm2, %xmm2
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; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vpsrad $6, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: sdiv8x32:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpsrad $31, %ymm0, %ymm1
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; AVX2-NEXT: vpsrld $26, %ymm1, %ymm1
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; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpsrad $6, %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%0 = sdiv <8 x i32> %var, <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64>
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ret <8 x i32> %0
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}
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define <16 x i16> @sdiv16x16(<16 x i16> %var) {
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; SSE-LABEL: sdiv16x16:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: psraw $15, %xmm2
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; SSE-NEXT: psrlw $14, %xmm2
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; SSE-NEXT: paddw %xmm0, %xmm2
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; SSE-NEXT: psraw $2, %xmm2
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; SSE-NEXT: movdqa %xmm1, %xmm3
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; SSE-NEXT: psraw $15, %xmm3
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; SSE-NEXT: psrlw $14, %xmm3
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; SSE-NEXT: paddw %xmm1, %xmm3
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; SSE-NEXT: psraw $2, %xmm3
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: movdqa %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: sdiv16x16:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpsraw $15, %xmm0, %xmm1
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; AVX1-NEXT: vpsrlw $14, %xmm1, %xmm1
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; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm1
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; AVX1-NEXT: vpsraw $2, %xmm1, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpsraw $15, %xmm0, %xmm2
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; AVX1-NEXT: vpsrlw $14, %xmm2, %xmm2
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; AVX1-NEXT: vpaddw %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vpsraw $2, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: sdiv16x16:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpsraw $15, %ymm0, %ymm1
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; AVX2-NEXT: vpsrlw $14, %ymm1, %ymm1
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; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpsraw $2, %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%a0 = sdiv <16 x i16> %var, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
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ret <16 x i16> %a0
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}
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; Div-by-0 in any lane is UB.
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define <4 x i32> @sdiv_non_splat(<4 x i32> %x) {
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; SSE-LABEL: sdiv_non_splat:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sdiv_non_splat:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0>
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ret <4 x i32> %y
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}
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