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171807f96b
Currently when cost of scalar operations is evaluated the vector type is used for scalar operations. Patch fixes this issue and fixes evaluation of the vector operations cost. Several test showed that vector cost model is too optimistic. It allowed vectorization of 8 or less add/fadd operations, though scalar code is faster. Actually, only for 16 or more operations vector code provides better performance. Differential Revision: https://reviews.llvm.org/D26277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288398 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
3.8 KiB
LLVM
67 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -debug < %s 2>&1 | FileCheck %s
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; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -debug < %s 2>&1 | FileCheck --check-prefix=SSE2 %s
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; REQUIRES: asserts
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; int test(unsigned int *p) {
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; int sum = 0;
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; for (int i = 0; i < 8; i++)
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; sum += p[i];
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; return sum;
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; }
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; Vector cost is 5, Scalar cost is 7
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; CHECK: Adding cost -2 for reduction that starts with %7 = load i32, i32* %arrayidx.7, align 4 (It is a splitting reduction)
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; Vector cost is 11, Scalar cost is 7
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; SSE2: Adding cost 4 for reduction that starts with %7 = load i32, i32* %arrayidx.7, align 4 (It is a splitting reduction)
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define i32 @test(i32* nocapture readonly %p) {
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; CHECK-LABEL: @test(
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; CHECK: [[BC:%.*]] = bitcast i32* %p to <8 x i32>*
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; CHECK-NEXT: [[LD:%.*]] = load <8 x i32>, <8 x i32>* [[BC]], align 4
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; CHECK: [[RDX_SHUF:%.*]] = shufflevector <8 x i32> [[LD]], <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = add <8 x i32> [[LD]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i32> [[BIN_RDX]], <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = add <8 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i32> [[BIN_RDX2]], <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX4:%.*]] = add <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
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; CHECK: ret i32 [[TMP2]]
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;
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; SSE2-LABEL: @test(
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; SSE2: [[BC:%.*]] = bitcast i32* %p to <8 x i32>*
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; SSE2-NEXT: [[LD:%.*]] = load <8 x i32>, <8 x i32>* [[BC]], align 4
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; SSE2: [[RDX_SHUF:%.*]] = shufflevector <8 x i32> [[LD]], <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE2-NEXT: [[BIN_RDX:%.*]] = add <8 x i32> [[LD]], [[RDX_SHUF]]
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; SSE2-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i32> [[BIN_RDX]], <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE2-NEXT: [[BIN_RDX2:%.*]] = add <8 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
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; SSE2-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i32> [[BIN_RDX2]], <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE2-NEXT: [[BIN_RDX4:%.*]] = add <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
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; SSE2-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
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; SSE2: ret i32 [[TMP2]]
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;
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entry:
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%0 = load i32, i32* %p, align 4
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%arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1
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%1 = load i32, i32* %arrayidx.1, align 4
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%mul.18 = add i32 %1, %0
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%arrayidx.2 = getelementptr inbounds i32, i32* %p, i64 2
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%2 = load i32, i32* %arrayidx.2, align 4
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%mul.29 = add i32 %2, %mul.18
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%arrayidx.3 = getelementptr inbounds i32, i32* %p, i64 3
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%3 = load i32, i32* %arrayidx.3, align 4
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%mul.310 = add i32 %3, %mul.29
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%arrayidx.4 = getelementptr inbounds i32, i32* %p, i64 4
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%4 = load i32, i32* %arrayidx.4, align 4
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%mul.411 = add i32 %4, %mul.310
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%arrayidx.5 = getelementptr inbounds i32, i32* %p, i64 5
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%5 = load i32, i32* %arrayidx.5, align 4
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%mul.512 = add i32 %5, %mul.411
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%arrayidx.6 = getelementptr inbounds i32, i32* %p, i64 6
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%6 = load i32, i32* %arrayidx.6, align 4
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%mul.613 = add i32 %6, %mul.512
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%arrayidx.7 = getelementptr inbounds i32, i32* %p, i64 7
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%7 = load i32, i32* %arrayidx.7, align 4
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%mul.714 = add i32 %7, %mul.613
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ret i32 %mul.714
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}
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