Matt Arsenault 0176ae243c AMDGPU: Switch some half using-tests to use amdhsa ...

The default clover ABI weirdly promotes half to float,
which should probably be fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333730 91177308-0d34-0410-b5e6-96231b3b80d8

2018-06-01 07:06:03 +00:00

..

AArch64

[AArch64] Reverted rL333427 fixing Clang UnitTest Failure

2018-05-31 08:27:53 +00:00

AMDGPU

AMDGPU: Switch some half using-tests to use amdhsa

2018-06-01 07:06:03 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] Enable SETCCCARRY lowering for Thumb1.

2018-05-29 18:17:16 +00:00

AVR

[AVR] Add a regression test for struct return lowering

2018-03-20 11:23:03 +00:00

BPF

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

Generic

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

Hexagon

[Hexagon] Use vector align-left when shift amount fits in 3 bits

2018-05-30 13:45:34 +00:00

Inputs

…

Lanai

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

[mips] Correct the predicates for a number of instructions.

2018-05-29 09:56:19 +00:00

MIR

[NFC] MIR-Canon: switching to a stable string sorting of instructions.

2018-05-13 06:07:20 +00:00

MSP430

Emit a left-shift instead of a power-of-two multiply for jump-tables

2018-05-16 08:58:26 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[DAG] fold FP binops with undef operands to NaN

2018-05-21 23:54:19 +00:00

PowerPC

[PowerPC] Fix the incorrect iterator inside peephole

2018-05-29 13:38:56 +00:00

RISCV

[RISCV] Add peepholes for Global Address lowering patterns

2018-05-29 19:34:54 +00:00

SPARC

[Sparc] Select correct register class for FP register constraints

2018-05-30 06:07:55 +00:00

SystemZ

[SystemZ] Bugfix in combineSTORE().

2018-05-25 09:01:23 +00:00

Thumb

Reapply ARM: Do not spill CSR to stack on entry to noreturn functions

2018-04-07 10:57:03 +00:00

Thumb2

[Thumb2] fix typo in test from r332548

2018-05-17 03:24:25 +00:00

WebAssembly

[WebAssembly] Update to the new names for the memory intrinsics.

2018-05-31 22:35:25 +00:00

WinCFGuard

Reland "Emit Function IDs table for Control Flow Guard"

2018-01-09 23:49:30 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

Relax GOTPCREL relocations for tail jmp instructions.

2018-05-31 18:12:33 +00:00

XCore

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00