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0719006e7e
This does not do what it is attempting to use it for and requires working around in LowerFormalArguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299667 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
5.7 KiB
TableGen
122 lines
5.7 KiB
TableGen
//===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the AMD Radeon GPUs.
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//
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//===----------------------------------------------------------------------===//
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// Inversion of CCIfInReg
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class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
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// Calling convention for SI
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def CC_SI : CallingConv<[
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CCIfInReg<CCIfType<[f32, i32, f16] , CCAssignToReg<[
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SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
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SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
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SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
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SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
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SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39
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]>>>,
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// We have no way of referring to the generated register tuples
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// here, so use a custom function.
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CCIfInReg<CCIfType<[i64], CCCustom<"allocateSGPRTuple">>>,
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CCIfByVal<CCIfType<[i64], CCCustom<"allocateSGPRTuple">>>,
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// 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs.
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CCIfNotInReg<CCIfType<[f32, i32, f16] , CCAssignToReg<[
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VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
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VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
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VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
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VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
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VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
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VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
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VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
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VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
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VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
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VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
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VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
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VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
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VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
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VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
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]>>>
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]>;
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def RetCC_SI : CallingConv<[
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CCIfType<[i32] , CCAssignToReg<[
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SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
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SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
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SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
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SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
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SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39
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]>>,
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// 32*4 + 4 is the minimum for a fetch shader with 32 outputs.
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CCIfType<[f32, f16] , CCAssignToReg<[
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VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
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VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
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VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
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VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
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VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
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VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
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VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
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VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
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VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
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VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
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VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
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VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
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VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
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VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
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]>>
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]>;
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// Calling convention for R600
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def CC_R600 : CallingConv<[
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CCIfInReg<CCIfType<[v4f32, v4i32] , CCAssignToReg<[
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T0_XYZW, T1_XYZW, T2_XYZW, T3_XYZW, T4_XYZW, T5_XYZW, T6_XYZW, T7_XYZW,
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T8_XYZW, T9_XYZW, T10_XYZW, T11_XYZW, T12_XYZW, T13_XYZW, T14_XYZW, T15_XYZW,
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T16_XYZW, T17_XYZW, T18_XYZW, T19_XYZW, T20_XYZW, T21_XYZW, T22_XYZW,
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T23_XYZW, T24_XYZW, T25_XYZW, T26_XYZW, T27_XYZW, T28_XYZW, T29_XYZW,
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T30_XYZW, T31_XYZW, T32_XYZW
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]>>>
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]>;
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// Calling convention for compute kernels
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def CC_AMDGPU_Kernel : CallingConv<[
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CCCustom<"allocateKernArg">
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]>;
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def CC_AMDGPU : CallingConv<[
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CCIf<"static_cast<const AMDGPUSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).getGeneration() >="
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"AMDGPUSubtarget::SOUTHERN_ISLANDS && "
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"!AMDGPU::isShader(State.getCallingConv())",
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CCDelegateTo<CC_AMDGPU_Kernel>>,
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CCIf<"static_cast<const AMDGPUSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).getGeneration() < "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS && "
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"!AMDGPU::isShader(State.getCallingConv())",
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CCDelegateTo<CC_AMDGPU_Kernel>>,
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CCIf<"static_cast<const AMDGPUSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).getGeneration() >= "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS",
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CCDelegateTo<CC_SI>>,
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CCIf<"static_cast<const AMDGPUSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).getGeneration() < "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS",
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CCDelegateTo<CC_R600>>
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]>;
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