mirror of
https://github.com/RPCS3/llvm.git
synced 2026-08-27 21:00:01 -04:00
Daniel Sanders
ed541fe200
Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250407 91177308-0d34-0410-b5e6-96231b3b80d8
136 lines
4.1 KiB
C++
136 lines
4.1 KiB
C++
//===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsABIInfo.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCTargetOptions.h"
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using namespace llvm;
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namespace {
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static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
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static const MCPhysReg Mips64IntRegs[8] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
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Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
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}
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ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
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if (IsO32())
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return makeArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return makeArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
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if (IsO32())
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return makeArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return makeArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
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if (IsO32())
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return CC != CallingConv::Fast ? 16 : 0;
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if (IsN32() || IsN64() || IsEABI())
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return 0;
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llvm_unreachable("Unhandled ABI");
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}
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MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
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const MCTargetOptions &Options) {
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if (Options.getABIName().startswith("o32"))
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return MipsABIInfo::O32();
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else if (Options.getABIName().startswith("n32"))
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return MipsABIInfo::N32();
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else if (Options.getABIName().startswith("n64"))
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return MipsABIInfo::N64();
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else if (Options.getABIName().startswith("eabi"))
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return MipsABIInfo::EABI();
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else if (!Options.getABIName().empty())
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llvm_unreachable("Unknown ABI option for MIPS");
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// FIXME: This shares code with the selectMipsCPU routine that's
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// used and not shared in a couple of other places. This needs unifying
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// at some level.
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if (CPU.empty() || CPU == "generic") {
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if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
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CPU = "mips32";
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else
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CPU = "mips64";
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}
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return StringSwitch<MipsABIInfo>(CPU)
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.Case("mips1", MipsABIInfo::O32())
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.Case("mips2", MipsABIInfo::O32())
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.Case("mips32", MipsABIInfo::O32())
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.Case("mips32r2", MipsABIInfo::O32())
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.Case("mips32r3", MipsABIInfo::O32())
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.Case("mips32r5", MipsABIInfo::O32())
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.Case("mips32r6", MipsABIInfo::O32())
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.Case("mips3", MipsABIInfo::N64())
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.Case("mips4", MipsABIInfo::N64())
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.Case("mips5", MipsABIInfo::N64())
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.Case("mips64", MipsABIInfo::N64())
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.Case("mips64r2", MipsABIInfo::N64())
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.Case("mips64r3", MipsABIInfo::N64())
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.Case("mips64r5", MipsABIInfo::N64())
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.Case("mips64r6", MipsABIInfo::N64())
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.Case("octeon", MipsABIInfo::N64())
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.Default(MipsABIInfo::Unknown());
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}
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unsigned MipsABIInfo::GetStackPtr() const {
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return ArePtrs64bit() ? Mips::SP_64 : Mips::SP;
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}
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unsigned MipsABIInfo::GetFramePtr() const {
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return ArePtrs64bit() ? Mips::FP_64 : Mips::FP;
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}
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unsigned MipsABIInfo::GetBasePtr() const {
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return ArePtrs64bit() ? Mips::S7_64 : Mips::S7;
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}
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unsigned MipsABIInfo::GetNullPtr() const {
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return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO;
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}
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unsigned MipsABIInfo::GetZeroReg() const {
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return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO;
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}
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unsigned MipsABIInfo::GetPtrAdduOp() const {
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return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;
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}
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unsigned MipsABIInfo::GetPtrAddiuOp() const {
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return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
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}
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unsigned MipsABIInfo::GetGPRMoveOp() const {
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return ArePtrs64bit() ? Mips::OR64 : Mips::OR;
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}
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unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
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static const unsigned EhDataReg[] = {
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Mips::A0, Mips::A1, Mips::A2, Mips::A3
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};
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static const unsigned EhDataReg64[] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
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};
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return IsN64() ? EhDataReg64[I] : EhDataReg[I];
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}
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