Arnold Schwaighofer 7e8cebf22d ARM cost model: Account for zero cost scalar SROA instructions ... By vectorizing a series of srl, or, ... instructions we have obfuscated the intention so much that the backend does not know how to fold this code away. radar://15336950 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193573 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-29 01:33:53 +00:00
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Hello	First check in. Modified a comment.	2013-09-27 07:36:10 +00:00
InstCombine	Remove x86_sse42_crc32_64_8 intrinsic. It has no functional difference from x86_sse42_crc32_32_8 and was not mapped to a clang builtin. I'm not even sure why this form of the instruction is even called out explicitly in the docs. Also add AutoUpgrade support to convert it into the other intrinsic with appropriate trunc and zext.	2013-10-15 05:20:47 +00:00
Instrumentation	fix PR17635: false positive with packed structures	2013-10-24 09:17:24 +00:00
IPO	Revert r193251 : Use address-taken to disambiguate global variable and indirect memops.	2013-10-27 03:08:44 +00:00
ObjCARC	Revert "Give internal classes hidden visibility."	2013-09-11 18:05:11 +00:00
Scalar	Fix SCEVExpander: don't try to expand quadratic recurrences outside a loop.	2013-10-25 21:35:56 +00:00
Utils	Quick look-up for block in loop.	2013-10-26 03:08:02 +00:00
Vectorize	ARM cost model: Account for zero cost scalar SROA instructions	2013-10-29 01:33:53 +00:00
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LLVMBuild.txt
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