Clement Courbet e6d7df955d [X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX. ...

Summary:
Starting from SNB, VZEROUPPER is handled by the renamer and uses no proc resources.
After HSW, it also has zero latency.

This fixes PR35606.

To reproduce:
Uops:
  llvm-exegesis -mode=uops -opcode-name=VZEROUPPER
Latency:
  echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper' | /tmp/llvm-exegesis -mode=latency -snippets-file=-
  echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper\naddps %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=latency -snippets-file=-

Reviewers: RKSimon, craig.topper, andreadb

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D54107

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346482 91177308-0d34-0410-b5e6-96231b3b80d8

2018-11-09 09:49:06 +00:00

..

AArch64

[COFF, ARM64] Add support for MSVC buffer security check

2018-11-09 02:48:36 +00:00

AMDGPU

Add test case for the regression caused by r344696

2018-11-08 18:01:38 +00:00

ARC

…

ARM

[ARM] Enable mixed types in ARM CGP

2018-11-09 09:28:27 +00:00

AVR

[AVR] Fix a backend bug that left extraneous operands after expansion

2018-11-05 05:49:04 +00:00

BPF

[bpf] Test case for symbol information in object file

2018-09-22 17:31:01 +00:00

Generic

Workaround PPC backend bug in test for r346322.

2018-11-07 17:01:47 +00:00

Hexagon

[Hexagon] Do not reduce load size for globals in small-data

2018-11-02 14:17:47 +00:00

Inputs

…

Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[DAGCombine] Improve alias analysis for chain of independent stores.

2018-11-08 19:14:20 +00:00

MIR

Add 'REQUIRES: default_triple' to test/CodeGen/MIR/X86/zero-probability.mir

2018-11-07 23:33:55 +00:00

MSP430

Revert "[MSP430] Add MC layer"

2018-11-08 16:21:29 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[NVPTX] Implement isLegalToVectorizeLoadChain

2018-08-27 17:29:43 +00:00

PowerPC

[Power9] Add support for stxvw4x.be and stxvd2x.be intrinsics

2018-11-05 17:31:26 +00:00

RISCV

[RISCV] Add some missing expansions for floating-point intrinsics

2018-11-02 19:50:38 +00:00

SPARC

Relax fast register allocator related test cases; NFC

2018-10-29 20:10:42 +00:00

SystemZ

[DAGCombine] Improve alias analysis for chain of independent stores.

2018-11-08 19:14:20 +00:00

Thumb

[ARM] Fix CPSR liveness in tMOVCCr_pseudo lowering.

2018-11-07 21:08:13 +00:00

Thumb2

[ARM] Enable spilling of the hGPR register class in Thumb2

2018-11-08 13:02:10 +00:00

WebAssembly

[WebAssembly] Lower select for vectors

2018-11-09 01:38:44 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX.

2018-11-09 09:49:06 +00:00

XCore

Relax fast register allocator related test cases; NFC

2018-10-29 20:10:42 +00:00