Craig Topper 359ff84264 [X86] Don't emit MULX by default with BMI2 ...

MULX has somewhat improved register allocation constraints compared to the legacy MUL instruction. Both output registers are encoded instead of fixed to EAX/EDX, but EDX is used as input. It also doesn't touch flags. Unfortunately, the encoding is longer.

Prefering it whenever BMI2 is enabled is probably not optimal. Choosing it should somehow be a function of register allocation constraints like converting adds to three address. gcc and icc definitely don't pick MULX by default. Not sure what if any rules they have for using it.

Differential Revision: https://reviews.llvm.org/D55565

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348975 91177308-0d34-0410-b5e6-96231b3b80d8

2018-12-12 21:21:31 +00:00

..

AArch64

Revert r348843 "[CodeGen] Allow mempcy/memset to generate small overlapping stores."

2018-12-11 13:38:43 +00:00

AMDGPU

[AMDGPU] Support for "uniform-work-group-size" attribute

2018-12-12 20:49:17 +00:00

ARC

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ARM

[ARM GlobalISel] Select load/store for Thumb2

2018-12-12 10:32:15 +00:00

AVR

[AVR] Reorder the CHECK lines in directmem.ll to match current trunk

2018-11-09 23:17:59 +00:00

BPF

[bpf] Test case for symbol information in object file

2018-09-22 17:31:01 +00:00

Generic

Move llc-start-stop-instance to x86

2018-12-04 18:19:08 +00:00

Hexagon

[Hexagon] Couple of fixes in optimize addressing mode

2018-12-10 21:56:04 +00:00

Inputs

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Lanai

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00

Mips

[TargetLowering] expandFP_TO_UINT - improve fp16 support

2018-11-19 19:16:13 +00:00

MIR

[CodeGen] Fix bugs in BranchFolderPass when debug labels are generated.

2018-11-30 08:07:29 +00:00

MSP430

[MSP430] Optimize srl/sra in case of A >> (8 + N)

2018-11-19 10:43:02 +00:00

Nios2

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NVPTX

[NVPTX] do not rely on cached subtarget info.

2018-12-12 18:31:04 +00:00

PowerPC

Revert r348843 "[CodeGen] Allow mempcy/memset to generate small overlapping stores."

2018-12-11 13:38:43 +00:00

RISCV

[RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases

2018-12-01 05:00:00 +00:00

SPARC

[Targets] Fixup incorrect targets in codemodel tests

2018-12-10 20:55:34 +00:00

SystemZ

[TargetLowering] Add ISD::AND handling to SimplifyDemandedVectorElts

2018-12-12 13:43:07 +00:00

Thumb

[SelectionDAG] swap select_cc operands to enable folding

2018-11-09 11:09:40 +00:00

Thumb2

[ARM] Enable spilling of the hGPR register class in Thumb2

2018-11-08 13:02:10 +00:00

WebAssembly

[WebAssembly] Add '.eventtype' directive support

2018-12-11 01:11:04 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[X86] Don't emit MULX by default with BMI2

2018-12-12 21:21:31 +00:00

XCore

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00