Igor Breger 7744f3ca3f AVX512: Implemented encoding and intrinsics for ...

vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11802

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247276 91177308-0d34-0410-b5e6-96231b3b80d8

2015-09-10 12:54:54 +00:00

..

AArch64

[llvm-readobj] MachO -- correctly dump section field 'Reserved3'

2015-09-01 16:29:02 +00:00

AMDGPU

AMDGPU/SI: Fix input vcc operand for VOP2b instructions

2015-09-08 21:15:00 +00:00

ARM

DI: Require subprogram definitions to be distinct

2015-08-28 20:26:49 +00:00

AsmParser

[MC/AsmParser] Avoid setting MCSymbol.IsUsed in some cases

2015-08-31 17:44:53 +00:00

COFF

[MC] Generate a timestamp for COFF object files

2015-09-01 23:46:11 +00:00

Disassembler

[mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions

2015-09-09 13:55:45 +00:00

ELF

[MC/ELF] Accept zero for .align directive

2015-09-08 18:59:47 +00:00

Hexagon

[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.

2015-06-05 16:00:11 +00:00

MachO

[MC] Convert all the remaining tests from macho-dump to llvm-readobj.

2015-09-10 01:50:00 +00:00

Markup

MC: Simple example parser for MC assembly markup.

2012-10-31 23:24:13 +00:00

Mips

[mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions

2015-09-09 13:55:45 +00:00

PowerPC

Scalar to vector conversions using direct moves

2015-08-13 17:40:44 +00:00

Sparc

Fix CHECK directives that weren't checking.

2015-08-31 21:10:35 +00:00

SystemZ

[SystemZ] Add z13 vector facility and MC support

2015-05-05 19:23:40 +00:00

X86

AVX512: Implemented encoding and intrinsics for

2015-09-10 12:54:54 +00:00