Matt Arsenault d2f17c4e2b Implement computeKnownBits for min/max nodes ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239378 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-09 00:52:41 +00:00

..

AArch64

[GlobalMerge] Take into account minsize on Global users' parents.

2015-06-04 20:39:23 +00:00

ARM

[ARM] Pass a callback to FunctionPass constructors to enable skipping execution

2015-06-08 18:50:43 +00:00

BPF

[bpf] rename triple names bpf_be -> bpfeb

2015-06-05 16:11:14 +00:00

CPP

[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction

2015-04-16 23:24:18 +00:00

Generic

Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).

2015-05-27 18:02:19 +00:00

Hexagon

[Hexagon] Adding functionality for searching for compound instruction pairs. Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions.

2015-06-08 16:34:47 +00:00

Inputs

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00

Mips

[mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.

2015-06-02 20:32:50 +00:00

MIR

MIR Serialization: use correct line and column numbers for LLVM IR errors.

2015-05-29 17:05:41 +00:00

MSP430

[opaque pointer type] Add textual IR support for explicit type parameter to gep operator

2015-03-13 18:20:45 +00:00

NVPTX

[NVPTX] run SROA after NVPTXFavorNonGenericAddrSpaces

2015-06-09 00:05:56 +00:00

PowerPC

Add support for VSX FMA single-precision instructions to the PPC back end

2015-05-29 17:13:25 +00:00

R600

Implement computeKnownBits for min/max nodes

2015-06-09 00:52:41 +00:00

SPARC

Add support for the Sparc implementation-defined "ASR" registers.

2015-05-18 16:29:48 +00:00

SystemZ

[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load

2015-05-05 19:34:10 +00:00

Thumb

Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM."

2015-06-05 18:01:28 +00:00

Thumb2

ARM: Thumb2 LDRD/STRD supports independent input/output regs

2015-06-03 16:30:24 +00:00

WinEH

[WinEH] C++ EH state numbering fixes

2015-05-20 23:22:24 +00:00

X86

[X86][SSE] Added lzcnt vector tests.

2015-06-08 19:58:43 +00:00

XCore

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00