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llvm/test/CodeGen
Chandler Carruth 07f0205ade [x86/SLH] Teach speculative load hardening to correctly harden the
indices used by AVX2 and AVX-512 gather instructions.

The index vector is hardened by broadcasting the predicate state
into a vector register and then or-ing. We don't even have to worry
about EFLAGS here.

I've added a test for all of the gather intrinsics to make sure that we
don't miss one. A particularly interesting creation is the gather
prefetch, which needs to be marked as potentially "loading" to get the
correct behavior. It's a memory access in many ways, and is actually
relevant for SLH. Based on discussion with Craig in review, I've moved
it to be `mayLoad` and `mayStore` rather than generic side effects. This
matches how we model other prefetch instructions.

Many thanks to Craig for the review here.

Differential Revision: https://reviews.llvm.org/D49336

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337144 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 04:17:51 +00:00
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2017-08-24 15:40:33 +00:00
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