llvm/CodeGen at 0a942dbb1e0f303191639498c35e742309f08a64 - llvm

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-01-19 00:14:20 +00:00

History

Evan Cheng 0a942dbb1e Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.

The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8

2010-05-19 01:08:17 +00:00

Alpha

Split big test into multiple directories to cater to

2010-04-07 20:43:35 +00:00

ARM

Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.

2010-05-19 01:08:17 +00:00

Blackfin

Start function numbering at 0.

2010-04-17 16:29:15 +00:00

CBackend

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