Chris Lattner 3f31d4304c These are now autogenerated ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23731 91177308-0d34-0410-b5e6-96231b3b80d8

2005-10-14 06:26:29 +00:00

..

Alpha

This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out

2005-10-09 20:11:35 +00:00

CBackend

fix CBackend/2005-09-27-VolatileFuncPtr.ll

2005-09-27 20:52:44 +00:00

IA64

Fix CodeGen/Generic/bool-to-double.ll

2005-10-07 04:50:48 +00:00

PowerPC

These are now autogenerated

2005-10-14 06:26:29 +00:00

Skeleton

CR registers are not used by this "target"

2005-09-30 06:43:58 +00:00

Sparc

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV8

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV9

silence a warning

2005-10-02 16:27:59 +00:00

X86

silence some warnings

2005-10-02 16:29:36 +00:00

Makefile

…

MRegisterInfo.cpp

Rename MRegisterDesc -> TargetRegisterDesc for consistency

2005-09-30 17:49:27 +00:00

SubtargetFeature.cpp

Print:

2005-09-07 05:44:14 +00:00

Target.td

Pull DAG ISel generation nodes out of the PowerPC backend to where they

2005-10-10 06:00:30 +00:00

TargetData.cpp

…

TargetFrameInfo.cpp

…

TargetInstrInfo.cpp

…

TargetMachine.cpp

…

TargetMachineRegistry.cpp

1. Use SubtargetFeatures in llc/lli.

2005-09-01 21:38:21 +00:00

TargetSchedInfo.cpp

…

TargetSelectionDAG.td

add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it

2005-10-14 04:55:10 +00:00

TargetSubtarget.cpp

…