mirror of
https://github.com/RPCS3/llvm.git
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0187e7a9ba
Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
748 lines
29 KiB
C++
748 lines
29 KiB
C++
//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower X86 MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "X86AsmPrinter.h"
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#include "InstPrinter/X86ATTInstPrinter.h"
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#include "X86COFFMachineModuleInfo.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/IR/Type.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Target/Mangler.h"
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using namespace llvm;
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namespace {
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/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
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class X86MCInstLower {
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MCContext &Ctx;
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Mangler *Mang;
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const MachineFunction &MF;
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const TargetMachine &TM;
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const MCAsmInfo &MAI;
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X86AsmPrinter &AsmPrinter;
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public:
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X86MCInstLower(Mangler *mang, const MachineFunction &MF,
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X86AsmPrinter &asmprinter);
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void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
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MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
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private:
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MachineModuleInfoMachO &getMachOMMI() const;
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};
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} // end anonymous namespace
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X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf,
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X86AsmPrinter &asmprinter)
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: Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()),
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MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
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MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
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return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
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}
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/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
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/// operand to an MCSymbol.
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MCSymbol *X86MCInstLower::
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GetSymbolFromOperand(const MachineOperand &MO) const {
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assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
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SmallString<128> Name;
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if (MO.isGlobal()) {
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const GlobalValue *GV = MO.getGlobal();
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bool isImplicitlyPrivate = false;
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if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
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MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
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MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
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MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
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isImplicitlyPrivate = true;
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Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
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} else if (MO.isSymbol()) {
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Name += MAI.getGlobalPrefix();
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Name += MO.getSymbolName();
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} else if (MO.isMBB()) {
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Name += MO.getMBB()->getSymbol()->getName();
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}
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// If the target flags on the operand changes the name of the symbol, do that
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// before we return the symbol.
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switch (MO.getTargetFlags()) {
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default: break;
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case X86II::MO_DLLIMPORT: {
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// Handle dllimport linkage.
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const char *Prefix = "__imp_";
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Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
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break;
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}
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case X86II::MO_DARWIN_NONLAZY:
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
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Name += "$non_lazy_ptr";
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MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
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MachineModuleInfoImpl::StubValueTy &StubSym =
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getMachOMMI().getGVStubEntry(Sym);
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if (StubSym.getPointer() == 0) {
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assert(MO.isGlobal() && "Extern symbol not handled yet");
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StubSym =
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MachineModuleInfoImpl::
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StubValueTy(Mang->getSymbol(MO.getGlobal()),
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!MO.getGlobal()->hasInternalLinkage());
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}
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return Sym;
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}
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
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Name += "$non_lazy_ptr";
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MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
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MachineModuleInfoImpl::StubValueTy &StubSym =
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getMachOMMI().getHiddenGVStubEntry(Sym);
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if (StubSym.getPointer() == 0) {
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assert(MO.isGlobal() && "Extern symbol not handled yet");
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StubSym =
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MachineModuleInfoImpl::
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StubValueTy(Mang->getSymbol(MO.getGlobal()),
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!MO.getGlobal()->hasInternalLinkage());
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}
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return Sym;
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}
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case X86II::MO_DARWIN_STUB: {
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Name += "$stub";
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MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
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MachineModuleInfoImpl::StubValueTy &StubSym =
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getMachOMMI().getFnStubEntry(Sym);
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if (StubSym.getPointer())
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return Sym;
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if (MO.isGlobal()) {
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StubSym =
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MachineModuleInfoImpl::
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StubValueTy(Mang->getSymbol(MO.getGlobal()),
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!MO.getGlobal()->hasInternalLinkage());
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} else {
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Name.erase(Name.end()-5, Name.end());
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StubSym =
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MachineModuleInfoImpl::
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StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
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}
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return Sym;
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}
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}
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return Ctx.GetOrCreateSymbol(Name.str());
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}
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MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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MCSymbol *Sym) const {
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// FIXME: We would like an efficient form for this, so we don't have to do a
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// lot of extra uniquing.
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const MCExpr *Expr = 0;
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MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
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switch (MO.getTargetFlags()) {
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default: llvm_unreachable("Unknown target flag on GV operand");
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case X86II::MO_NO_FLAG: // No flag.
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// These affect the name of the symbol, not any suffix.
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case X86II::MO_DARWIN_NONLAZY:
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case X86II::MO_DLLIMPORT:
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case X86II::MO_DARWIN_STUB:
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break;
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case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
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case X86II::MO_TLVP_PIC_BASE:
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Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
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// Subtract the pic base.
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Expr = MCBinaryExpr::CreateSub(Expr,
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MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
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Ctx),
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Ctx);
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break;
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case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
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case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
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case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
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case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
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case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
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case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
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case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
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case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
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case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
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case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
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case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
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case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
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case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
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case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
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case X86II::MO_PIC_BASE_OFFSET:
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
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Expr = MCSymbolRefExpr::Create(Sym, Ctx);
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// Subtract the pic base.
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Expr = MCBinaryExpr::CreateSub(Expr,
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MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
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Ctx);
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if (MO.isJTI() && MAI.hasSetDirective()) {
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// If .set directive is supported, use it to reduce the number of
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// relocations the assembler will generate for differences between
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// local labels. This is only safe when the symbols are in the same
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// section so we are restricting it to jumptable references.
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MCSymbol *Label = Ctx.CreateTempSymbol();
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AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
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Expr = MCSymbolRefExpr::Create(Label, Ctx);
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}
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break;
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}
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if (Expr == 0)
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Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
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if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
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Expr = MCBinaryExpr::CreateAdd(Expr,
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MCConstantExpr::Create(MO.getOffset(), Ctx),
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Ctx);
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return MCOperand::CreateExpr(Expr);
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}
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/// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
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static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
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OutMI.setOpcode(NewOpc);
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OutMI.addOperand(OutMI.getOperand(0));
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OutMI.addOperand(OutMI.getOperand(0));
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}
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/// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
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/// a short fixed-register form.
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static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
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unsigned ImmOp = Inst.getNumOperands() - 1;
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assert(Inst.getOperand(0).isReg() &&
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(Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
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((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
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Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
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Inst.getNumOperands() == 2) && "Unexpected instruction!");
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// Check whether the destination register can be fixed.
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unsigned Reg = Inst.getOperand(0).getReg();
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if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
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return;
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// If so, rewrite the instruction.
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MCOperand Saved = Inst.getOperand(ImmOp);
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Inst = MCInst();
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Inst.setOpcode(Opcode);
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Inst.addOperand(Saved);
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}
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/// \brief Simplify things like MOV32rm to MOV32o32a.
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static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
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unsigned Opcode) {
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// Don't make these simplifications in 64-bit mode; other assemblers don't
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// perform them because they make the code larger.
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if (Printer.getSubtarget().is64Bit())
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return;
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bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
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unsigned AddrBase = IsStore;
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unsigned RegOp = IsStore ? 0 : 5;
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unsigned AddrOp = AddrBase + 3;
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assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
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Inst.getOperand(AddrBase + 0).isReg() && // base
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Inst.getOperand(AddrBase + 1).isImm() && // scale
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Inst.getOperand(AddrBase + 2).isReg() && // index register
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(Inst.getOperand(AddrOp).isExpr() || // address
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Inst.getOperand(AddrOp).isImm())&&
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Inst.getOperand(AddrBase + 4).isReg() && // segment
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"Unexpected instruction!");
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// Check whether the destination register can be fixed.
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unsigned Reg = Inst.getOperand(RegOp).getReg();
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if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
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return;
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// Check whether this is an absolute address.
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// FIXME: We know TLVP symbol refs aren't, but there should be a better way
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// to do this here.
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bool Absolute = true;
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if (Inst.getOperand(AddrOp).isExpr()) {
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const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
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if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
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if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
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Absolute = false;
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}
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if (Absolute &&
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(Inst.getOperand(AddrBase + 0).getReg() != 0 ||
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Inst.getOperand(AddrBase + 2).getReg() != 0 ||
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Inst.getOperand(AddrBase + 4).getReg() != 0 ||
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Inst.getOperand(AddrBase + 1).getImm() != 1))
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return;
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// If so, rewrite the instruction.
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MCOperand Saved = Inst.getOperand(AddrOp);
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Inst = MCInst();
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Inst.setOpcode(Opcode);
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Inst.addOperand(Saved);
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}
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void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp;
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switch (MO.getType()) {
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default:
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MI->dump();
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit()) continue;
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MCOp = MCOperand::CreateReg(MO.getReg());
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break;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::CreateImm(MO.getImm());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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case MachineOperand::MO_GlobalAddress:
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case MachineOperand::MO_ExternalSymbol:
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MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = LowerSymbolOperand(MO,
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AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
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break;
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case MachineOperand::MO_RegisterMask:
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// Ignore call clobbers.
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continue;
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}
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OutMI.addOperand(MCOp);
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}
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// Handle a few special cases to eliminate operand modifiers.
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ReSimplify:
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switch (OutMI.getOpcode()) {
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case X86::LEA64_32r:
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case X86::LEA64r:
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case X86::LEA16r:
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case X86::LEA32r:
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// LEA should have a segment register, but it must be empty.
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assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
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"Unexpected # of LEA operands");
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assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
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"LEA has segment specified!");
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break;
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case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
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case X86::MOV32ri64:
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OutMI.setOpcode(X86::MOV32ri);
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break;
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// Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
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// if one of the registers is extended, but other isn't.
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case X86::VMOVAPDrr:
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case X86::VMOVAPDYrr:
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case X86::VMOVAPSrr:
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case X86::VMOVAPSYrr:
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case X86::VMOVDQArr:
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case X86::VMOVDQAYrr:
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case X86::VMOVDQUrr:
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case X86::VMOVDQUYrr:
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case X86::VMOVUPDrr:
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case X86::VMOVUPDYrr:
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case X86::VMOVUPSrr:
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case X86::VMOVUPSYrr: {
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if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
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X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
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unsigned NewOpc;
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switch (OutMI.getOpcode()) {
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default: llvm_unreachable("Invalid opcode");
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case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
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case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
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case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
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case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
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case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
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case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
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case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
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case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
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case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
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case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
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case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
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case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
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}
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OutMI.setOpcode(NewOpc);
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}
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break;
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}
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case X86::VMOVSDrr:
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case X86::VMOVSSrr: {
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if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
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X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
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unsigned NewOpc;
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switch (OutMI.getOpcode()) {
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default: llvm_unreachable("Invalid opcode");
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case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
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case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
|
|
}
|
|
OutMI.setOpcode(NewOpc);
|
|
}
|
|
break;
|
|
}
|
|
|
|
// TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
|
|
// inputs modeled as normal uses instead of implicit uses. As such, truncate
|
|
// off all but the first operand (the callee). FIXME: Change isel.
|
|
case X86::TAILJMPr64:
|
|
case X86::CALL64r:
|
|
case X86::CALL64pcrel32: {
|
|
unsigned Opcode = OutMI.getOpcode();
|
|
MCOperand Saved = OutMI.getOperand(0);
|
|
OutMI = MCInst();
|
|
OutMI.setOpcode(Opcode);
|
|
OutMI.addOperand(Saved);
|
|
break;
|
|
}
|
|
|
|
case X86::EH_RETURN:
|
|
case X86::EH_RETURN64: {
|
|
OutMI = MCInst();
|
|
OutMI.setOpcode(X86::RET);
|
|
break;
|
|
}
|
|
|
|
// TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
|
|
case X86::TAILJMPr:
|
|
case X86::TAILJMPd:
|
|
case X86::TAILJMPd64: {
|
|
unsigned Opcode;
|
|
switch (OutMI.getOpcode()) {
|
|
default: llvm_unreachable("Invalid opcode");
|
|
case X86::TAILJMPr: Opcode = X86::JMP32r; break;
|
|
case X86::TAILJMPd:
|
|
case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
|
|
}
|
|
|
|
MCOperand Saved = OutMI.getOperand(0);
|
|
OutMI = MCInst();
|
|
OutMI.setOpcode(Opcode);
|
|
OutMI.addOperand(Saved);
|
|
break;
|
|
}
|
|
|
|
// These are pseudo-ops for OR to help with the OR->ADD transformation. We do
|
|
// this with an ugly goto in case the resultant OR uses EAX and needs the
|
|
// short form.
|
|
case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
|
|
case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
|
|
case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
|
|
case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
|
|
case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
|
|
case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
|
|
case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
|
|
case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
|
|
case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
|
|
|
|
// The assembler backend wants to see branches in their small form and relax
|
|
// them to their large form. The JIT can only handle the large form because
|
|
// it does not do relaxation. For now, translate the large form to the
|
|
// small one here.
|
|
case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
|
|
case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
|
|
case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
|
|
case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
|
|
case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
|
|
case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
|
|
case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
|
|
case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
|
|
case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
|
|
case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
|
|
case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
|
|
case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
|
|
case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
|
|
case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
|
|
case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
|
|
case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
|
|
case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
|
|
|
|
// Atomic load and store require a separate pseudo-inst because Acquire
|
|
// implies mayStore and Release implies mayLoad; fix these to regular MOV
|
|
// instructions here
|
|
case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
|
|
case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
|
|
case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
|
|
case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
|
|
case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
|
|
case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
|
|
case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
|
|
case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
|
|
|
|
// We don't currently select the correct instruction form for instructions
|
|
// which have a short %eax, etc. form. Handle this by custom lowering, for
|
|
// now.
|
|
//
|
|
// Note, we are currently not handling the following instructions:
|
|
// MOV64ao8, MOV64o8a
|
|
// XCHG16ar, XCHG32ar, XCHG64ar
|
|
case X86::MOV8mr_NOREX:
|
|
case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
|
|
case X86::MOV8rm_NOREX:
|
|
case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
|
|
case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
|
|
case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
|
|
case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
|
|
case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
|
|
|
|
case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
|
|
case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
|
|
case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
|
|
case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
|
|
case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
|
|
case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
|
|
case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
|
|
case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
|
|
case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
|
|
case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
|
|
case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
|
|
case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
|
|
case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
|
|
case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
|
|
case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
|
|
case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
|
|
case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
|
|
case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
|
|
case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
|
|
case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
|
|
case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
|
|
case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
|
|
case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
|
|
case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
|
|
case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
|
|
case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
|
|
case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
|
|
case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
|
|
case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
|
|
case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
|
|
case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
|
|
case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
|
|
case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
|
|
case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
|
|
case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
|
|
case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
|
|
|
|
case X86::MORESTACK_RET:
|
|
OutMI.setOpcode(X86::RET);
|
|
break;
|
|
|
|
case X86::MORESTACK_RET_RESTORE_R10:
|
|
OutMI.setOpcode(X86::MOV64rr);
|
|
OutMI.addOperand(MCOperand::CreateReg(X86::R10));
|
|
OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
|
|
|
|
AsmPrinter.OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void LowerTlsAddr(MCStreamer &OutStreamer,
|
|
X86MCInstLower &MCInstLowering,
|
|
const MachineInstr &MI) {
|
|
|
|
bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
|
|
MI.getOpcode() == X86::TLS_base_addr64;
|
|
|
|
bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
|
|
|
|
MCContext &context = OutStreamer.getContext();
|
|
|
|
if (needsPadding)
|
|
OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
|
|
|
|
MCSymbolRefExpr::VariantKind SRVK;
|
|
switch (MI.getOpcode()) {
|
|
case X86::TLS_addr32:
|
|
case X86::TLS_addr64:
|
|
SRVK = MCSymbolRefExpr::VK_TLSGD;
|
|
break;
|
|
case X86::TLS_base_addr32:
|
|
SRVK = MCSymbolRefExpr::VK_TLSLDM;
|
|
break;
|
|
case X86::TLS_base_addr64:
|
|
SRVK = MCSymbolRefExpr::VK_TLSLD;
|
|
break;
|
|
default:
|
|
llvm_unreachable("unexpected opcode");
|
|
}
|
|
|
|
MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
|
|
const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
|
|
|
|
MCInst LEA;
|
|
if (is64Bits) {
|
|
LEA.setOpcode(X86::LEA64r);
|
|
LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
|
|
LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
|
|
LEA.addOperand(MCOperand::CreateImm(1)); // scale
|
|
LEA.addOperand(MCOperand::CreateReg(0)); // index
|
|
LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
|
|
LEA.addOperand(MCOperand::CreateReg(0)); // seg
|
|
} else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
|
|
LEA.setOpcode(X86::LEA32r);
|
|
LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
|
|
LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
|
|
LEA.addOperand(MCOperand::CreateImm(1)); // scale
|
|
LEA.addOperand(MCOperand::CreateReg(0)); // index
|
|
LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
|
|
LEA.addOperand(MCOperand::CreateReg(0)); // seg
|
|
} else {
|
|
LEA.setOpcode(X86::LEA32r);
|
|
LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
|
|
LEA.addOperand(MCOperand::CreateReg(0)); // base
|
|
LEA.addOperand(MCOperand::CreateImm(1)); // scale
|
|
LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
|
|
LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
|
|
LEA.addOperand(MCOperand::CreateReg(0)); // seg
|
|
}
|
|
OutStreamer.EmitInstruction(LEA);
|
|
|
|
if (needsPadding) {
|
|
OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
|
|
OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
|
|
OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX));
|
|
}
|
|
|
|
StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
|
|
MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
|
|
const MCSymbolRefExpr *tlsRef =
|
|
MCSymbolRefExpr::Create(tlsGetAddr,
|
|
MCSymbolRefExpr::VK_PLT,
|
|
context);
|
|
|
|
OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
|
|
: X86::CALLpcrel32)
|
|
.addExpr(tlsRef));
|
|
}
|
|
|
|
void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
|
X86MCInstLower MCInstLowering(Mang, *MF, *this);
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::DBG_VALUE:
|
|
llvm_unreachable("Should be handled target independently");
|
|
|
|
// Emit nothing here but a comment if we can.
|
|
case X86::Int_MemBarrier:
|
|
if (OutStreamer.hasRawTextSupport())
|
|
OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
|
|
return;
|
|
|
|
|
|
case X86::EH_RETURN:
|
|
case X86::EH_RETURN64: {
|
|
// Lower these as normal, but add some comments.
|
|
unsigned Reg = MI->getOperand(0).getReg();
|
|
OutStreamer.AddComment(StringRef("eh_return, addr: %") +
|
|
X86ATTInstPrinter::getRegisterName(Reg));
|
|
break;
|
|
}
|
|
case X86::TAILJMPr:
|
|
case X86::TAILJMPd:
|
|
case X86::TAILJMPd64:
|
|
// Lower these as normal, but add some comments.
|
|
OutStreamer.AddComment("TAILCALL");
|
|
break;
|
|
|
|
case X86::TLS_addr32:
|
|
case X86::TLS_addr64:
|
|
case X86::TLS_base_addr32:
|
|
case X86::TLS_base_addr64:
|
|
return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
|
|
|
|
case X86::MOVPC32r: {
|
|
// This is a pseudo op for a two instruction sequence with a label, which
|
|
// looks like:
|
|
// call "L1$pb"
|
|
// "L1$pb":
|
|
// popl %esi
|
|
|
|
// Emit the call.
|
|
MCSymbol *PICBase = MF->getPICBaseSymbol();
|
|
// FIXME: We would like an efficient form for this, so we don't have to do a
|
|
// lot of extra uniquing.
|
|
OutStreamer.EmitInstruction(MCInstBuilder(X86::CALLpcrel32)
|
|
.addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
|
|
|
|
// Emit the label.
|
|
OutStreamer.EmitLabel(PICBase);
|
|
|
|
// popl $reg
|
|
OutStreamer.EmitInstruction(MCInstBuilder(X86::POP32r)
|
|
.addReg(MI->getOperand(0).getReg()));
|
|
return;
|
|
}
|
|
|
|
case X86::ADD32ri: {
|
|
// Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
|
|
if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
|
|
break;
|
|
|
|
// Okay, we have something like:
|
|
// EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
|
|
|
|
// For this, we want to print something like:
|
|
// MYGLOBAL + (. - PICBASE)
|
|
// However, we can't generate a ".", so just emit a new label here and refer
|
|
// to it.
|
|
MCSymbol *DotSym = OutContext.CreateTempSymbol();
|
|
OutStreamer.EmitLabel(DotSym);
|
|
|
|
// Now that we have emitted the label, lower the complex operand expression.
|
|
MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
|
|
|
|
const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
|
|
const MCExpr *PICBase =
|
|
MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
|
|
DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
|
|
|
|
DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
|
|
DotExpr, OutContext);
|
|
|
|
OutStreamer.EmitInstruction(MCInstBuilder(X86::ADD32ri)
|
|
.addReg(MI->getOperand(0).getReg())
|
|
.addReg(MI->getOperand(1).getReg())
|
|
.addExpr(DotExpr));
|
|
return;
|
|
}
|
|
}
|
|
|
|
MCInst TmpInst;
|
|
MCInstLowering.Lower(MI, TmpInst);
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|