mirror of
https://github.com/RPCS3/llvm.git
synced 2025-01-09 13:41:47 +00:00
9a3e49a1b3
Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16639 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
2.3 KiB
Makefile
58 lines
2.3 KiB
Makefile
##===- lib/Target/X86/Makefile -----------------------------*- Makefile -*-===##
|
|
#
|
|
# The LLVM Compiler Infrastructure
|
|
#
|
|
# This file was developed by the LLVM research group and is distributed under
|
|
# the University of Illinois Open Source License. See LICENSE.TXT for details.
|
|
#
|
|
##===----------------------------------------------------------------------===##
|
|
LEVEL = ../../..
|
|
LIBRARYNAME = x86
|
|
include $(LEVEL)/Makefile.common
|
|
|
|
TARGET = X86
|
|
|
|
# Make sure that tblgen is run, first thing.
|
|
$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
|
|
X86GenRegisterInfo.inc X86GenInstrNames.inc \
|
|
X86GenInstrInfo.inc X86GenATTAsmWriter.inc \
|
|
X86GenIntelAsmWriter.inc
|
|
|
|
TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
|
|
$(SourceDir)/../Target.td
|
|
|
|
$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
|
|
@echo "Building $(TARGET).td register names with tblgen"
|
|
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
|
|
|
|
$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
|
|
@echo "Building $(TARGET).td register information header with tblgen"
|
|
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
|
|
|
|
$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
|
|
@echo "Building $(TARGET).td register info implementation with tblgen"
|
|
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
|
|
|
|
$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
|
|
@echo "Building $(TARGET).td instruction names with tblgen"
|
|
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
|
|
|
|
$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
|
|
@echo "Building $(TARGET).td instruction information with tblgen"
|
|
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
|
|
|
|
$(TARGET)GenATTAsmWriter.inc:: $(TDFILES) $(TBLGEN)
|
|
@echo "Building $(TARGET).td AT&T assembly writer with tblgen"
|
|
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@
|
|
|
|
$(TARGET)GenIntelAsmWriter.inc:: $(TDFILES) $(TBLGEN)
|
|
@echo "Building $(TARGET).td Intel assembly writer with tblgen"
|
|
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -asmwriternum=1 -o $@
|
|
|
|
#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
|
|
# @echo "Building $(TARGET).td instruction selector with tblgen"
|
|
# $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
|
|
|
|
clean::
|
|
$(VERB) rm -f *.inc
|