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Code Issues Packages Projects Releases 10 Wiki Activity
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107362cf5f2ce05e87e43cda247aa741137cedfe
llvm/test/CodeGen/MIR
T
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Tom Stellard 107362cf5f RegAllocGreedy: Properly initialize this pass, so that -run-pass will work
Reviewers: qcolombet, MatzeB

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D26572

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286895 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-14 21:50:13 +00:00
..
AArch64
Add AArch64 unit tests
2016-10-12 09:00:44 +00:00
AMDGPU
AMDGPU: Implement SGPR spilling with scalar stores
2016-11-13 18:20:54 +00:00
ARM
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
2016-08-25 01:27:13 +00:00
Generic
RegAllocGreedy: Properly initialize this pass, so that -run-pass will work
2016-11-14 21:50:13 +00:00
Hexagon
[MIRParser] Parse lane masks for register live-ins
2016-10-12 21:06:45 +00:00
Lanai
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
2016-08-25 01:27:13 +00:00
Mips
MIRParser: Use shorter cfi identifiers
2016-07-26 18:20:00 +00:00
NVPTX
llc: Add support for -run-pass none
2016-07-16 02:24:59 +00:00
PowerPC
MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.
2016-08-24 01:32:41 +00:00
X86
MIRParser: Rewrite register info initialization; mostly NFC
2016-10-11 03:13:01 +00:00
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