Petr Pavlu 10c750cc3f [ARM] Enable spilling of the hGPR register class in Thumb2 ...

Generalize code in Thumb2InstrInfo::storeRegToStackSlot() and
loadRegToStackSlot() to allow the GPR class or any of its sub-classes
(including hGPR) to be stored/loaded by ARM::t2STRi12/ARM::t2LDRi12.

Differential Revision: https://reviews.llvm.org/D51927


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346401 91177308-0d34-0410-b5e6-96231b3b80d8

2018-11-08 13:02:10 +00:00

..

AArch64

[AArch64] [Windows] Trap after noreturn calls.

2018-11-07 21:31:14 +00:00

AMDGPU

[AMDGPU] Extend promote alloca vectorization

2018-11-08 00:16:23 +00:00

ARC

…

ARM

[ARM] Fix CPSR liveness in tMOVCCr_pseudo lowering.

2018-11-07 21:08:13 +00:00

AVR

[AVR] Fix a backend bug that left extraneous operands after expansion

2018-11-05 05:49:04 +00:00

BPF

[bpf] Test case for symbol information in object file

2018-09-22 17:31:01 +00:00

Generic

Workaround PPC backend bug in test for r346322.

2018-11-07 17:01:47 +00:00

Hexagon

[Hexagon] Do not reduce load size for globals in small-data

2018-11-02 14:17:47 +00:00

Inputs

…

Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[MIPS GlobalISel] Set operand order for G_MERGE and G_UNMERGE

2018-11-07 11:45:43 +00:00

MIR

Add 'REQUIRES: default_triple' to test/CodeGen/MIR/X86/zero-probability.mir

2018-11-07 23:33:55 +00:00

MSP430

[MSP430] Add MC layer

2018-11-08 00:03:45 +00:00

Nios2

…

NVPTX

[NVPTX] Implement isLegalToVectorizeLoadChain

2018-08-27 17:29:43 +00:00

PowerPC

[Power9] Add support for stxvw4x.be and stxvd2x.be intrinsics

2018-11-05 17:31:26 +00:00

RISCV

[RISCV] Add some missing expansions for floating-point intrinsics

2018-11-02 19:50:38 +00:00

SPARC

Relax fast register allocator related test cases; NFC

2018-10-29 20:10:42 +00:00

SystemZ

[SchedModel] Fix for read advance cycles with implicit pseudo operands.

2018-10-30 15:04:40 +00:00

Thumb

[ARM] Fix CPSR liveness in tMOVCCr_pseudo lowering.

2018-11-07 21:08:13 +00:00

Thumb2

[ARM] Enable spilling of the hGPR register class in Thumb2

2018-11-08 13:02:10 +00:00

WebAssembly

[WebAssembly] Add V128 to WebAssemblyInstrInfo::copyPhysReg

2018-11-08 02:35:28 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[X86][AVX] Tidyup prefixes and regenerate interleaved tests

2018-11-08 12:14:10 +00:00

XCore

Relax fast register allocator related test cases; NFC

2018-10-29 20:10:42 +00:00