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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
107 lines
3.4 KiB
C++
107 lines
3.4 KiB
C++
//===-- AMDIL.h - Top-level interface for AMDIL representation --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// This file contains the entry points for global functions defined in the LLVM
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/// AMDGPU back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDIL_H
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#define AMDIL_H
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Target/TargetMachine.h"
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#define ARENA_SEGMENT_RESERVED_UAVS 12
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#define DEFAULT_ARENA_UAV_ID 8
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#define DEFAULT_RAW_UAV_ID 7
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#define GLOBAL_RETURN_RAW_UAV_ID 11
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#define HW_MAX_NUM_CB 8
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#define MAX_NUM_UNIQUE_UAVS 8
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#define OPENCL_MAX_NUM_ATOMIC_COUNTERS 8
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#define OPENCL_MAX_READ_IMAGES 128
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#define OPENCL_MAX_WRITE_IMAGES 8
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#define OPENCL_MAX_SAMPLERS 16
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// The next two values can never be zero, as zero is the ID that is
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// used to assert against.
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#define DEFAULT_LDS_ID 1
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#define DEFAULT_GDS_ID 1
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#define DEFAULT_SCRATCH_ID 1
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#define DEFAULT_VEC_SLOTS 8
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#define OCL_DEVICE_RV710 0x0001
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#define OCL_DEVICE_RV730 0x0002
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#define OCL_DEVICE_RV770 0x0004
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#define OCL_DEVICE_CEDAR 0x0008
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#define OCL_DEVICE_REDWOOD 0x0010
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#define OCL_DEVICE_JUNIPER 0x0020
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#define OCL_DEVICE_CYPRESS 0x0040
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#define OCL_DEVICE_CAICOS 0x0080
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#define OCL_DEVICE_TURKS 0x0100
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#define OCL_DEVICE_BARTS 0x0200
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#define OCL_DEVICE_CAYMAN 0x0400
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#define OCL_DEVICE_ALL 0x3FFF
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/// The number of function ID's that are reserved for
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/// internal compiler usage.
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const unsigned int RESERVED_FUNCS = 1024;
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namespace llvm {
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class AMDGPUInstrPrinter;
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class FunctionPass;
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class MCAsmInfo;
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class raw_ostream;
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class Target;
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class TargetMachine;
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// Instruction selection passes.
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FunctionPass*
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createAMDGPUISelDag(TargetMachine &TM);
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FunctionPass*
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createAMDGPUPeepholeOpt(TargetMachine &TM);
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// Pre emit passes.
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FunctionPass*
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createAMDGPUCFGPreparationPass(TargetMachine &TM);
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FunctionPass*
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createAMDGPUCFGStructurizerPass(TargetMachine &TM);
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extern Target TheAMDGPUTarget;
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} // end namespace llvm;
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// Include device information enumerations
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#include "AMDILDeviceInfo.h"
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namespace llvm {
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/// OpenCL uses address spaces to differentiate between
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/// various memory regions on the hardware. On the CPU
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/// all of the address spaces point to the same memory,
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/// however on the GPU, each address space points to
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/// a seperate piece of memory that is unique from other
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/// memory locations.
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namespace AMDGPUAS {
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enum AddressSpaces {
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PRIVATE_ADDRESS = 0, ///< Address space for private memory.
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GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
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CONSTANT_ADDRESS = 2, ///< Address space for constant memory.
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LOCAL_ADDRESS = 3, ///< Address space for local memory.
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REGION_ADDRESS = 4, ///< Address space for region memory.
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ADDRESS_NONE = 5, ///< Address space for unknown memory.
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PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
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PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
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USER_SGPR_ADDRESS = 8, ///< Address space for USER_SGPRS on SI
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LAST_ADDRESS = 9
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};
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} // namespace AMDGPUAS
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} // end namespace llvm
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#endif // AMDIL_H
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