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c4a24ae263
This patch corresponds to review: http://reviews.llvm.org/D17711 It disables direct moves on these operations in 32-bit mode since the patterns assume 64-bit registers. The final patch is slightly different from the Phabricator review as the bitcast operations needed to be disabled in 32-bit mode as well. This fixes PR26617. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264282 91177308-0d34-0410-b5e6-96231b3b80d8
16 lines
357 B
LLVM
16 lines
357 B
LLVM
; RUN: llc -mcpu=pwr8 -mtriple=powerpc-unknown-unknown < %s | FileCheck %s
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define i32 @test(<4 x i32> %v, i32 %elem) #0 {
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entry:
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%vecext = extractelement <4 x i32> %v, i32 %elem
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ret i32 %vecext
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}
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; CHECK: stxvw4x 34,
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; CHECK: lwzx 3,
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define float @test2(i32 signext %a) {
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entry:
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%conv = bitcast i32 %a to float
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ret float %conv
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}
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; CHECK-NOT: mtvsr
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