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34963650b8
This patch attempts to represent a shuffle as a repeating shuffle (recognisable by is128BitLaneRepeatedShuffleMask) with the source input(s) in their original lanes, followed by a single permutation of the 128-bit lanes to their final destinations. On AVX2 we can additionally attempt to match using 64-bit sub-lane permutation. AVX2 can also now match a similar 'broadcasted' repeating shuffle. This patch has several benefits: * Avoids prematurely matching with lowerVectorShuffleByMerging128BitLanes which can require both inputs to have their input lanes permuted before shuffling. * Can replace PERMPS/PERMD instructions - although these are useful for cross-lane unary shuffling, they require their shuffle mask to be pre-loaded (and increase register pressure). * Matching the repeating shuffle makes use of a lot of existing shuffle lowering. There is an outstanding minor AVX1 regression (combine_unneeded_subvector1 in vector-shuffle-combining.ll) of a previously 128-bit shuffle + subvector splat being converted to a subvector splat + (2 instruction) 256-bit shuffle, I intend to fix this in a followup patch for review. Differential Revision: http://reviews.llvm.org/D16537 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260834 91177308-0d34-0410-b5e6-96231b3b80d8
153 lines
4.7 KiB
LLVM
153 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
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define <4 x i32> @trunc4(<4 x i64> %A) nounwind {
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; CHECK-LABEL: trunc4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,0,2,4,6,4,6]
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; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,2,3]
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%B = trunc <4 x i64> %A to <4 x i32>
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ret <4 x i32>%B
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}
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define <8 x i16> @trunc8(<8 x i32> %A) nounwind {
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; CHECK-LABEL: trunc8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero
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; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%B = trunc <8 x i32> %A to <8 x i16>
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ret <8 x i16>%B
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}
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define <4 x i64> @sext4(<4 x i32> %A) nounwind {
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; CHECK-LABEL: sext4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxdq %xmm0, %ymm0
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; CHECK-NEXT: retq
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%B = sext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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define <8 x i32> @sext8(<8 x i16> %A) nounwind {
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; CHECK-LABEL: sext8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0
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; CHECK-NEXT: retq
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%B = sext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <4 x i64> @zext4(<4 x i32> %A) nounwind {
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; CHECK-LABEL: zext4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; CHECK-NEXT: retq
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%B = zext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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define <8 x i32> @zext8(<8 x i16> %A) nounwind {
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; CHECK-LABEL: zext8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; CHECK-NEXT: retq
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%B = zext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <8 x i32> @zext_8i8_8i32(<8 x i8> %A) nounwind {
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; CHECK-LABEL: zext_8i8_8i32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; CHECK-NEXT: retq
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%B = zext <8 x i8> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <16 x i16> @zext_16i8_16i16(<16 x i8> %z) {
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; CHECK-LABEL: zext_16i8_16i16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
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; CHECK-NEXT: retq
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%t = zext <16 x i8> %z to <16 x i16>
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ret <16 x i16> %t
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}
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define <16 x i16> @sext_16i8_16i16(<16 x i8> %z) {
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; CHECK-LABEL: sext_16i8_16i16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxbw %xmm0, %ymm0
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; CHECK-NEXT: retq
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%t = sext <16 x i8> %z to <16 x i16>
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ret <16 x i16> %t
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}
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define <16 x i8> @trunc_16i16_16i8(<16 x i16> %z) {
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; CHECK-LABEL: trunc_16i16_16i8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
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; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
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; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1
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; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0
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; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%t = trunc <16 x i16> %z to <16 x i8>
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ret <16 x i8> %t
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}
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define <4 x i64> @load_sext_test1(<4 x i32> *%ptr) {
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; CHECK-LABEL: load_sext_test1:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxdq (%rdi), %ymm0
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; CHECK-NEXT: retq
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%X = load <4 x i32>, <4 x i32>* %ptr
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%Y = sext <4 x i32> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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define <4 x i64> @load_sext_test2(<4 x i8> *%ptr) {
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; CHECK-LABEL: load_sext_test2:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxbq (%rdi), %ymm0
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; CHECK-NEXT: retq
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%X = load <4 x i8>, <4 x i8>* %ptr
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%Y = sext <4 x i8> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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define <4 x i64> @load_sext_test3(<4 x i16> *%ptr) {
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; CHECK-LABEL: load_sext_test3:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxwq (%rdi), %ymm0
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; CHECK-NEXT: retq
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%X = load <4 x i16>, <4 x i16>* %ptr
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%Y = sext <4 x i16> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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define <8 x i32> @load_sext_test4(<8 x i16> *%ptr) {
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; CHECK-LABEL: load_sext_test4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxwd (%rdi), %ymm0
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; CHECK-NEXT: retq
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%X = load <8 x i16>, <8 x i16>* %ptr
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%Y = sext <8 x i16> %X to <8 x i32>
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ret <8 x i32>%Y
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}
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define <8 x i32> @load_sext_test5(<8 x i8> *%ptr) {
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; CHECK-LABEL: load_sext_test5:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxbd (%rdi), %ymm0
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; CHECK-NEXT: retq
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%X = load <8 x i8>, <8 x i8>* %ptr
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%Y = sext <8 x i8> %X to <8 x i32>
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ret <8 x i32>%Y
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}
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