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9c3a9de18e
Tidied up triple and regenerate tests using update_llc_test_checks.py git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254060 91177308-0d34-0410-b5e6-96231b3b80d8
207 lines
7.6 KiB
LLVM
207 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
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; Check constant loads of every 128-bit and 256-bit vector type
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; for size optimization using splat ops available with AVX and AVX2.
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; There is no AVX broadcast from double to 128-bit vector because movddup has been around since SSE3 (grrr).
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define <2 x double> @splat_v2f64(<2 x double> %x) #0 {
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; CHECK-LABEL: splat_v2f64:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
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; CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%add = fadd <2 x double> %x, <double 1.0, double 1.0>
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ret <2 x double> %add
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}
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define <4 x double> @splat_v4f64(<4 x double> %x) #1 {
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; CHECK-LABEL: splat_v4f64:
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; CHECK: # BB#0:
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; CHECK-NEXT: vbroadcastsd {{.*}}(%rip), %ymm1
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; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%add = fadd <4 x double> %x, <double 1.0, double 1.0, double 1.0, double 1.0>
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ret <4 x double> %add
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}
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define <4 x float> @splat_v4f32(<4 x float> %x) #0 {
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; CHECK-LABEL: splat_v4f32:
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; CHECK: # BB#0:
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; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
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; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%add = fadd <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
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ret <4 x float> %add
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}
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define <8 x float> @splat_v8f32(<8 x float> %x) #1 {
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; CHECK-LABEL: splat_v8f32:
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; CHECK: # BB#0:
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; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
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; CHECK-NEXT: vaddps %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%add = fadd <8 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>
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ret <8 x float> %add
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}
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; AVX can't do integer splats, so fake it: use vmovddup to splat 64-bit value.
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; We also generate vmovddup for AVX2 because it's one byte smaller than vpbroadcastq.
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define <2 x i64> @splat_v2i64(<2 x i64> %x) #1 {
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; CHECK-LABEL: splat_v2i64:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
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; CHECK-NEXT: vpaddq %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%add = add <2 x i64> %x, <i64 1, i64 1>
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ret <2 x i64> %add
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}
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; AVX can't do 256-bit integer ops, so we split this into two 128-bit vectors,
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; and then we fake it: use vmovddup to splat 64-bit value.
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define <4 x i64> @splat_v4i64(<4 x i64> %x) #0 {
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; AVX-LABEL: splat_v4i64:
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; AVX: # BB#0:
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX-NEXT: vmovddup {{.*#+}} xmm2 = mem[0,0]
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; AVX-NEXT: vpaddq %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vpaddq %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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; AVX2-LABEL: splat_v4i64:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastq {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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%add = add <4 x i64> %x, <i64 1, i64 1, i64 1, i64 1>
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ret <4 x i64> %add
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}
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; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
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define <4 x i32> @splat_v4i32(<4 x i32> %x) #1 {
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; AVX-LABEL: splat_v4i32:
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; AVX: # BB#0:
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; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; AVX2-LABEL: splat_v4i32:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
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; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%add = add <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
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define <8 x i32> @splat_v8i32(<8 x i32> %x) #0 {
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; AVX-LABEL: splat_v8i32:
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; AVX: # BB#0:
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm2
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; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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; AVX2-LABEL: splat_v8i32:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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%add = add <8 x i32> %x, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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ret <8 x i32> %add
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}
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; AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
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define <8 x i16> @splat_v8i16(<8 x i16> %x) #1 {
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; AVX-LABEL: splat_v8i16:
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; AVX: # BB#0:
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; AVX-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; AVX2-LABEL: splat_v8i16:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastw {{.*}}(%rip), %xmm1
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; AVX2-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%add = add <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <8 x i16> %add
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}
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; AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
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define <16 x i16> @splat_v16i16(<16 x i16> %x) #0 {
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; AVX-LABEL: splat_v16i16:
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; AVX: # BB#0:
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1]
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; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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; AVX2-LABEL: splat_v16i16:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastw {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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%add = add <16 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <16 x i16> %add
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}
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; AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
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define <16 x i8> @splat_v16i8(<16 x i8> %x) #1 {
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; AVX-LABEL: splat_v16i8:
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; AVX: # BB#0:
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; AVX-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; AVX2-LABEL: splat_v16i8:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastb {{.*}}(%rip), %xmm1
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; AVX2-NEXT: vpaddb %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%add = add <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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ret <16 x i8> %add
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}
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; AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
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define <32 x i8> @splat_v32i8(<32 x i8> %x) #0 {
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; AVX-LABEL: splat_v32i8:
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; AVX: # BB#0:
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
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; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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; AVX2-LABEL: splat_v32i8:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastb {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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%add = add <32 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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ret <32 x i8> %add
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}
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; PR23259: Verify that ISel doesn't crash with a 'fatal error in backend'
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; due to a missing AVX pattern to select a v2i64 X86ISD::BROADCAST of a
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; loadi64 with multiple uses.
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@A = common global <3 x i64> zeroinitializer, align 32
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define <8 x i64> @pr23259() #1 {
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entry:
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%0 = load <4 x i64>, <4 x i64>* bitcast (<3 x i64>* @A to <4 x i64>*), align 32
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%1 = shufflevector <4 x i64> %0, <4 x i64> undef, <3 x i32> <i32 undef, i32 undef, i32 2>
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%shuffle = shufflevector <3 x i64> <i64 1, i64 undef, i64 undef>, <3 x i64> %1, <8 x i32> <i32 5, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i64> %shuffle
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}
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attributes #0 = { optsize }
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attributes #1 = { minsize }
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