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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41810 91177308-0d34-0410-b5e6-96231b3b80d8
1211 lines
31 KiB
Plaintext
1211 lines
31 KiB
Plaintext
//===---------------------------------------------------------------------===//
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// Random ideas for the X86 backend.
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//===---------------------------------------------------------------------===//
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Missing features:
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- Support for SSE4: http://www.intel.com/software/penryn
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http://softwarecommunity.intel.com/isn/Downloads/Intel%20SSE4%20Programming%20Reference.pdf
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- support for 3DNow!
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- weird abis?
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//===---------------------------------------------------------------------===//
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Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
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Hi and Lo parts (combination of MUL and MULH[SU] into one node). Add this to
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X86, & make the dag combiner produce it when needed. This will eliminate one
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imul from the code generated for:
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long long test(long long X, long long Y) { return X*Y; }
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by using the EAX result from the mul. We should add a similar node for
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DIVREM.
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another case is:
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long long test(int X, int Y) { return (long long)X*Y; }
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... which should only be one imul instruction.
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or:
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unsigned long long int t2(unsigned int a, unsigned int b) {
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return (unsigned long long)a * b;
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}
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... which should be one mul instruction.
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This can be done with a custom expander, but it would be nice to move this to
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generic code.
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//===---------------------------------------------------------------------===//
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CodeGen/X86/lea-3.ll:test3 should be a single LEA, not a shift/move. The X86
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backend knows how to three-addressify this shift, but it appears the register
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allocator isn't even asking it to do so in this case. We should investigate
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why this isn't happening, it could have significant impact on other important
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cases for X86 as well.
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//===---------------------------------------------------------------------===//
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This should be one DIV/IDIV instruction, not a libcall:
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unsigned test(unsigned long long X, unsigned Y) {
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return X/Y;
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}
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This can be done trivially with a custom legalizer. What about overflow
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though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
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//===---------------------------------------------------------------------===//
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Improvements to the multiply -> shift/add algorithm:
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http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
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//===---------------------------------------------------------------------===//
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Improve code like this (occurs fairly frequently, e.g. in LLVM):
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long long foo(int x) { return 1LL << x; }
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
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Another useful one would be ~0ULL >> X and ~0ULL << X.
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One better solution for 1LL << x is:
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xorl %eax, %eax
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xorl %edx, %edx
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testb $32, %cl
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sete %al
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setne %dl
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sall %cl, %eax
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sall %cl, %edx
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But that requires good 8-bit subreg support.
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64-bit shifts (in general) expand to really bad code. Instead of using
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cmovs, we should expand to a conditional branch like GCC produces.
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//===---------------------------------------------------------------------===//
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Compile this:
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_Bool f(_Bool a) { return a!=1; }
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into:
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movzbl %dil, %eax
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xorl $1, %eax
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ret
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//===---------------------------------------------------------------------===//
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Some isel ideas:
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1. Dynamic programming based approach when compile time if not an
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issue.
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2. Code duplication (addressing mode) during isel.
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3. Other ideas from "Register-Sensitive Selection, Duplication, and
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Sequencing of Instructions".
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4. Scheduling for reduced register pressure. E.g. "Minimum Register
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Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
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and other related papers.
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http://citeseer.ist.psu.edu/govindarajan01minimum.html
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//===---------------------------------------------------------------------===//
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Should we promote i16 to i32 to avoid partial register update stalls?
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//===---------------------------------------------------------------------===//
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Leave any_extend as pseudo instruction and hint to register
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allocator. Delay codegen until post register allocation.
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//===---------------------------------------------------------------------===//
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Count leading zeros and count trailing zeros:
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int clz(int X) { return __builtin_clz(X); }
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int ctz(int X) { return __builtin_ctz(X); }
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$ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
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clz:
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bsr %eax, DWORD PTR [%esp+4]
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xor %eax, 31
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ret
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ctz:
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bsf %eax, DWORD PTR [%esp+4]
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ret
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however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
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aren't.
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Another example (use predsimplify to eliminate a select):
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int foo (unsigned long j) {
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if (j)
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return __builtin_ffs (j) - 1;
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else
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return 0;
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}
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//===---------------------------------------------------------------------===//
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It appears icc use push for parameter passing. Need to investigate.
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//===---------------------------------------------------------------------===//
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Only use inc/neg/not instructions on processors where they are faster than
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add/sub/xor. They are slower on the P4 due to only updating some processor
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flags.
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//===---------------------------------------------------------------------===//
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The instruction selector sometimes misses folding a load into a compare. The
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pattern is written as (cmp reg, (load p)). Because the compare isn't
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commutative, it is not matched with the load on both sides. The dag combiner
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should be made smart enough to cannonicalize the load into the RHS of a compare
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when it can invert the result of the compare for free.
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//===---------------------------------------------------------------------===//
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How about intrinsics? An example is:
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*res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C));
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compiles to
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pmuludq (%eax), %xmm0
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movl 8(%esp), %eax
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movdqa (%eax), %xmm1
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pmulhuw %xmm0, %xmm1
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The transformation probably requires a X86 specific pass or a DAG combiner
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target specific hook.
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//===---------------------------------------------------------------------===//
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In many cases, LLVM generates code like this:
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_test:
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movl 8(%esp), %eax
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cmpl %eax, 4(%esp)
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setl %al
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movzbl %al, %eax
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ret
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on some processors (which ones?), it is more efficient to do this:
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_test:
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movl 8(%esp), %ebx
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xor %eax, %eax
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cmpl %ebx, 4(%esp)
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setl %al
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ret
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Doing this correctly is tricky though, as the xor clobbers the flags.
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//===---------------------------------------------------------------------===//
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We should generate bts/btr/etc instructions on targets where they are cheap or
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when codesize is important. e.g., for:
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void setbit(int *target, int bit) {
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*target |= (1 << bit);
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}
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void clearbit(int *target, int bit) {
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*target &= ~(1 << bit);
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}
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//===---------------------------------------------------------------------===//
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Instead of the following for memset char*, 1, 10:
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movl $16843009, 4(%edx)
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movl $16843009, (%edx)
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movw $257, 8(%edx)
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It might be better to generate
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movl $16843009, %eax
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movl %eax, 4(%edx)
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movl %eax, (%edx)
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movw al, 8(%edx)
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when we can spare a register. It reduces code size.
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//===---------------------------------------------------------------------===//
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Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
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get this:
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int %test1(int %X) {
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%Y = div int %X, 8
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ret int %Y
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}
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_test1:
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movl 4(%esp), %eax
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movl %eax, %ecx
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sarl $31, %ecx
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shrl $29, %ecx
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addl %ecx, %eax
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sarl $3, %eax
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ret
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GCC knows several different ways to codegen it, one of which is this:
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_test1:
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movl 4(%esp), %eax
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cmpl $-1, %eax
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leal 7(%eax), %ecx
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cmovle %ecx, %eax
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sarl $3, %eax
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ret
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which is probably slower, but it's interesting at least :)
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//===---------------------------------------------------------------------===//
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The first BB of this code:
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declare bool %foo()
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int %bar() {
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%V = call bool %foo()
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br bool %V, label %T, label %F
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T:
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ret int 1
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F:
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call bool %foo()
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ret int 12
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}
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compiles to:
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_bar:
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subl $12, %esp
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call L_foo$stub
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xorb $1, %al
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testb %al, %al
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jne LBB_bar_2 # F
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It would be better to emit "cmp %al, 1" than a xor and test.
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//===---------------------------------------------------------------------===//
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Enable X86InstrInfo::convertToThreeAddress().
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//===---------------------------------------------------------------------===//
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We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
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We should leave these as libcalls for everything over a much lower threshold,
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since libc is hand tuned for medium and large mem ops (avoiding RFO for large
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stores, TLB preheating, etc)
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//===---------------------------------------------------------------------===//
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Optimize this into something reasonable:
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x * copysign(1.0, y) * copysign(1.0, z)
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//===---------------------------------------------------------------------===//
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Optimize copysign(x, *y) to use an integer load from y.
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//===---------------------------------------------------------------------===//
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%X = weak global int 0
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void %foo(int %N) {
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%N = cast int %N to uint
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%tmp.24 = setgt int %N, 0
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br bool %tmp.24, label %no_exit, label %return
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no_exit:
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%indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
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%i.0.0 = cast uint %indvar to int
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volatile store int %i.0.0, int* %X
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%indvar.next = add uint %indvar, 1
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%exitcond = seteq uint %indvar.next, %N
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br bool %exitcond, label %return, label %no_exit
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return:
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ret void
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}
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compiles into:
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.text
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.align 4
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.globl _foo
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_foo:
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movl 4(%esp), %eax
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cmpl $1, %eax
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jl LBB_foo_4 # return
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LBB_foo_1: # no_exit.preheader
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xorl %ecx, %ecx
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LBB_foo_2: # no_exit
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movl L_X$non_lazy_ptr, %edx
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movl %ecx, (%edx)
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incl %ecx
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cmpl %eax, %ecx
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jne LBB_foo_2 # no_exit
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LBB_foo_3: # return.loopexit
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LBB_foo_4: # return
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ret
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We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
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remateralization is implemented. This can be accomplished with 1) a target
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dependent LICM pass or 2) makeing SelectDAG represent the whole function.
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//===---------------------------------------------------------------------===//
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The following tests perform worse with LSR:
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lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
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//===---------------------------------------------------------------------===//
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We are generating far worse code than gcc:
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volatile short X, Y;
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void foo(int N) {
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int i;
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for (i = 0; i < N; i++) { X = i; Y = i*4; }
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}
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LBB1_1: #bb.preheader
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xorl %ecx, %ecx
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xorw %dx, %dx
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LBB1_2: #bb
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movl L_X$non_lazy_ptr, %esi
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movw %dx, (%esi)
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movw %dx, %si
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shlw $2, %si
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movl L_Y$non_lazy_ptr, %edi
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movw %si, (%edi)
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incl %ecx
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incw %dx
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cmpl %eax, %ecx
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jne LBB1_2 #bb
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vs.
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xorl %edx, %edx
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movl L_X$non_lazy_ptr-"L00000000001$pb"(%ebx), %esi
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movl L_Y$non_lazy_ptr-"L00000000001$pb"(%ebx), %ecx
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L4:
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movw %dx, (%esi)
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leal 0(,%edx,4), %eax
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movw %ax, (%ecx)
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addl $1, %edx
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cmpl %edx, %edi
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jne L4
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There are 3 issues:
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1. Lack of post regalloc LICM.
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2. LSR unable to reused IV for a different type (i16 vs. i32) even though
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the cast would be free.
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//===---------------------------------------------------------------------===//
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Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
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FR64 to VR128.
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//===---------------------------------------------------------------------===//
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mov $reg, 48(%esp)
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...
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leal 48(%esp), %eax
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mov %eax, (%esp)
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call _foo
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Obviously it would have been better for the first mov (or any op) to store
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directly %esp[0] if there are no other uses.
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//===---------------------------------------------------------------------===//
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Adding to the list of cmp / test poor codegen issues:
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int test(__m128 *A, __m128 *B) {
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if (_mm_comige_ss(*A, *B))
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return 3;
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else
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return 4;
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}
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_test:
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movl 8(%esp), %eax
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movaps (%eax), %xmm0
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movl 4(%esp), %eax
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movaps (%eax), %xmm1
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comiss %xmm0, %xmm1
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setae %al
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movzbl %al, %ecx
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movl $3, %eax
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movl $4, %edx
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cmpl $0, %ecx
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cmove %edx, %eax
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ret
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Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
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are a number of issues. 1) We are introducing a setcc between the result of the
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intrisic call and select. 2) The intrinsic is expected to produce a i32 value
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so a any extend (which becomes a zero extend) is added.
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We probably need some kind of target DAG combine hook to fix this.
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//===---------------------------------------------------------------------===//
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We generate significantly worse code for this than GCC:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
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http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
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There is also one case we do worse on PPC.
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//===---------------------------------------------------------------------===//
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If shorter, we should use things like:
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movzwl %ax, %eax
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instead of:
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andl $65535, %EAX
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The former can also be used when the two-addressy nature of the 'and' would
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require a copy to be inserted (in X86InstrInfo::convertToThreeAddress).
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//===---------------------------------------------------------------------===//
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Consider this:
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typedef struct pair { float A, B; } pair;
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void pairtest(pair P, float *FP) {
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*FP = P.A+P.B;
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}
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We currently generate this code with llvmgcc4:
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_pairtest:
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movl 8(%esp), %eax
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movl 4(%esp), %ecx
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movd %eax, %xmm0
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movd %ecx, %xmm1
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addss %xmm0, %xmm1
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movl 12(%esp), %eax
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movss %xmm1, (%eax)
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ret
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we should be able to generate:
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_pairtest:
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movss 4(%esp), %xmm0
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movl 12(%esp), %eax
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addss 8(%esp), %xmm0
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movss %xmm0, (%eax)
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ret
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The issue is that llvmgcc4 is forcing the struct to memory, then passing it as
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integer chunks. It does this so that structs like {short,short} are passed in
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a single 32-bit integer stack slot. We should handle the safe cases above much
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nicer, while still handling the hard cases.
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While true in general, in this specific case we could do better by promoting
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load int + bitcast to float -> load fload. This basically needs alignment info,
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the code is already implemented (but disabled) in dag combine).
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//===---------------------------------------------------------------------===//
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Another instruction selector deficiency:
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void %bar() {
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%tmp = load int (int)** %foo
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%tmp = tail call int %tmp( int 3 )
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ret void
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}
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_bar:
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subl $12, %esp
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movl L_foo$non_lazy_ptr, %eax
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movl (%eax), %eax
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call *%eax
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addl $12, %esp
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ret
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The current isel scheme will not allow the load to be folded in the call since
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the load's chain result is read by the callseq_start.
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//===---------------------------------------------------------------------===//
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For this:
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int test(int a)
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{
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return a * 3;
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}
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We currently emits
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imull $3, 4(%esp), %eax
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Perhaps this is what we really should generate is? Is imull three or four
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cycles? Note: ICC generates this:
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movl 4(%esp), %eax
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leal (%eax,%eax,2), %eax
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The current instruction priority is based on pattern complexity. The former is
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more "complex" because it folds a load so the latter will not be emitted.
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Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
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should always try to match LEA first since the LEA matching code does some
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|
estimate to determine whether the match is profitable.
|
|
|
|
However, if we care more about code size, then imull is better. It's two bytes
|
|
shorter than movl + leal.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Implement CTTZ, CTLZ with bsf and bsr. GCC produces:
|
|
|
|
int ctz_(unsigned X) { return __builtin_ctz(X); }
|
|
int clz_(unsigned X) { return __builtin_clz(X); }
|
|
int ffs_(unsigned X) { return __builtin_ffs(X); }
|
|
|
|
_ctz_:
|
|
bsfl 4(%esp), %eax
|
|
ret
|
|
_clz_:
|
|
bsrl 4(%esp), %eax
|
|
xorl $31, %eax
|
|
ret
|
|
_ffs_:
|
|
movl $-1, %edx
|
|
bsfl 4(%esp), %eax
|
|
cmove %edx, %eax
|
|
addl $1, %eax
|
|
ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
It appears gcc place string data with linkonce linkage in
|
|
.section __TEXT,__const_coal,coalesced instead of
|
|
.section __DATA,__const_coal,coalesced.
|
|
Take a look at darwin.h, there are other Darwin assembler directives that we
|
|
do not make use of.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
int %foo(int* %a, int %t) {
|
|
entry:
|
|
br label %cond_true
|
|
|
|
cond_true: ; preds = %cond_true, %entry
|
|
%x.0.0 = phi int [ 0, %entry ], [ %tmp9, %cond_true ]
|
|
%t_addr.0.0 = phi int [ %t, %entry ], [ %tmp7, %cond_true ]
|
|
%tmp2 = getelementptr int* %a, int %x.0.0
|
|
%tmp3 = load int* %tmp2 ; <int> [#uses=1]
|
|
%tmp5 = add int %t_addr.0.0, %x.0.0 ; <int> [#uses=1]
|
|
%tmp7 = add int %tmp5, %tmp3 ; <int> [#uses=2]
|
|
%tmp9 = add int %x.0.0, 1 ; <int> [#uses=2]
|
|
%tmp = setgt int %tmp9, 39 ; <bool> [#uses=1]
|
|
br bool %tmp, label %bb12, label %cond_true
|
|
|
|
bb12: ; preds = %cond_true
|
|
ret int %tmp7
|
|
}
|
|
|
|
is pessimized by -loop-reduce and -indvars
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
u32 to float conversion improvement:
|
|
|
|
float uint32_2_float( unsigned u ) {
|
|
float fl = (int) (u & 0xffff);
|
|
float fh = (int) (u >> 16);
|
|
fh *= 0x1.0p16f;
|
|
return fh + fl;
|
|
}
|
|
|
|
00000000 subl $0x04,%esp
|
|
00000003 movl 0x08(%esp,1),%eax
|
|
00000007 movl %eax,%ecx
|
|
00000009 shrl $0x10,%ecx
|
|
0000000c cvtsi2ss %ecx,%xmm0
|
|
00000010 andl $0x0000ffff,%eax
|
|
00000015 cvtsi2ss %eax,%xmm1
|
|
00000019 mulss 0x00000078,%xmm0
|
|
00000021 addss %xmm1,%xmm0
|
|
00000025 movss %xmm0,(%esp,1)
|
|
0000002a flds (%esp,1)
|
|
0000002d addl $0x04,%esp
|
|
00000030 ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
When using fastcc abi, align stack slot of argument of type double on 8 byte
|
|
boundary to improve performance.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Codegen:
|
|
|
|
int f(int a, int b) {
|
|
if (a == 4 || a == 6)
|
|
b++;
|
|
return b;
|
|
}
|
|
|
|
|
|
as:
|
|
|
|
or eax, 2
|
|
cmp eax, 6
|
|
jz label
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
|
|
simplifications for integer "x cmp y ? a : b". For example, instead of:
|
|
|
|
int G;
|
|
void f(int X, int Y) {
|
|
G = X < 0 ? 14 : 13;
|
|
}
|
|
|
|
compiling to:
|
|
|
|
_f:
|
|
movl $14, %eax
|
|
movl $13, %ecx
|
|
movl 4(%esp), %edx
|
|
testl %edx, %edx
|
|
cmovl %eax, %ecx
|
|
movl %ecx, _G
|
|
ret
|
|
|
|
it could be:
|
|
_f:
|
|
movl 4(%esp), %eax
|
|
sarl $31, %eax
|
|
notl %eax
|
|
addl $14, %eax
|
|
movl %eax, _G
|
|
ret
|
|
|
|
etc.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Currently we don't have elimination of redundant stack manipulations. Consider
|
|
the code:
|
|
|
|
int %main() {
|
|
entry:
|
|
call fastcc void %test1( )
|
|
call fastcc void %test2( sbyte* cast (void ()* %test1 to sbyte*) )
|
|
ret int 0
|
|
}
|
|
|
|
declare fastcc void %test1()
|
|
|
|
declare fastcc void %test2(sbyte*)
|
|
|
|
|
|
This currently compiles to:
|
|
|
|
subl $16, %esp
|
|
call _test5
|
|
addl $12, %esp
|
|
subl $16, %esp
|
|
movl $_test5, (%esp)
|
|
call _test6
|
|
addl $12, %esp
|
|
|
|
The add\sub pair is really unneeded here.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
We currently compile sign_extend_inreg into two shifts:
|
|
|
|
long foo(long X) {
|
|
return (long)(signed char)X;
|
|
}
|
|
|
|
becomes:
|
|
|
|
_foo:
|
|
movl 4(%esp), %eax
|
|
shll $24, %eax
|
|
sarl $24, %eax
|
|
ret
|
|
|
|
This could be:
|
|
|
|
_foo:
|
|
movsbl 4(%esp),%eax
|
|
ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Consider the expansion of:
|
|
|
|
uint %test3(uint %X) {
|
|
%tmp1 = rem uint %X, 255
|
|
ret uint %tmp1
|
|
}
|
|
|
|
Currently it compiles to:
|
|
|
|
...
|
|
movl $2155905153, %ecx
|
|
movl 8(%esp), %esi
|
|
movl %esi, %eax
|
|
mull %ecx
|
|
...
|
|
|
|
This could be "reassociated" into:
|
|
|
|
movl $2155905153, %eax
|
|
movl 8(%esp), %ecx
|
|
mull %ecx
|
|
|
|
to avoid the copy. In fact, the existing two-address stuff would do this
|
|
except that mul isn't a commutative 2-addr instruction. I guess this has
|
|
to be done at isel time based on the #uses to mul?
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Make sure the instruction which starts a loop does not cross a cacheline
|
|
boundary. This requires knowning the exact length of each machine instruction.
|
|
That is somewhat complicated, but doable. Example 256.bzip2:
|
|
|
|
In the new trace, the hot loop has an instruction which crosses a cacheline
|
|
boundary. In addition to potential cache misses, this can't help decoding as I
|
|
imagine there has to be some kind of complicated decoder reset and realignment
|
|
to grab the bytes from the next cacheline.
|
|
|
|
532 532 0x3cfc movb (1809(%esp, %esi), %bl <<<--- spans 2 64 byte lines
|
|
942 942 0x3d03 movl %dh, (1809(%esp, %esi)
|
|
937 937 0x3d0a incl %esi
|
|
3 3 0x3d0b cmpb %bl, %dl
|
|
27 27 0x3d0d jnz 0x000062db <main+11707>
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
This could be a single 16-bit load.
|
|
|
|
int f(char *p) {
|
|
if ((p[0] == 1) & (p[1] == 2)) return 1;
|
|
return 0;
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
We should inline lrintf and probably other libc functions.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Start using the flags more. For example, compile:
|
|
|
|
int add_zf(int *x, int y, int a, int b) {
|
|
if ((*x += y) == 0)
|
|
return a;
|
|
else
|
|
return b;
|
|
}
|
|
|
|
to:
|
|
addl %esi, (%rdi)
|
|
movl %edx, %eax
|
|
cmovne %ecx, %eax
|
|
ret
|
|
instead of:
|
|
|
|
_add_zf:
|
|
addl (%rdi), %esi
|
|
movl %esi, (%rdi)
|
|
testl %esi, %esi
|
|
cmove %edx, %ecx
|
|
movl %ecx, %eax
|
|
ret
|
|
|
|
and:
|
|
|
|
int add_zf(int *x, int y, int a, int b) {
|
|
if ((*x + y) < 0)
|
|
return a;
|
|
else
|
|
return b;
|
|
}
|
|
|
|
to:
|
|
|
|
add_zf:
|
|
addl (%rdi), %esi
|
|
movl %edx, %eax
|
|
cmovns %ecx, %eax
|
|
ret
|
|
|
|
instead of:
|
|
|
|
_add_zf:
|
|
addl (%rdi), %esi
|
|
testl %esi, %esi
|
|
cmovs %edx, %ecx
|
|
movl %ecx, %eax
|
|
ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
This:
|
|
#include <math.h>
|
|
int foo(double X) { return isnan(X); }
|
|
|
|
compiles to (-m64):
|
|
|
|
_foo:
|
|
pxor %xmm1, %xmm1
|
|
ucomisd %xmm1, %xmm0
|
|
setp %al
|
|
movzbl %al, %eax
|
|
ret
|
|
|
|
the pxor is not needed, we could compare the value against itself.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
These two functions have identical effects:
|
|
|
|
unsigned int f(unsigned int i, unsigned int n) {++i; if (i == n) ++i; return i;}
|
|
unsigned int f2(unsigned int i, unsigned int n) {++i; i += i == n; return i;}
|
|
|
|
We currently compile them to:
|
|
|
|
_f:
|
|
movl 4(%esp), %eax
|
|
movl %eax, %ecx
|
|
incl %ecx
|
|
movl 8(%esp), %edx
|
|
cmpl %edx, %ecx
|
|
jne LBB1_2 #UnifiedReturnBlock
|
|
LBB1_1: #cond_true
|
|
addl $2, %eax
|
|
ret
|
|
LBB1_2: #UnifiedReturnBlock
|
|
movl %ecx, %eax
|
|
ret
|
|
_f2:
|
|
movl 4(%esp), %eax
|
|
movl %eax, %ecx
|
|
incl %ecx
|
|
cmpl 8(%esp), %ecx
|
|
sete %cl
|
|
movzbl %cl, %ecx
|
|
leal 1(%ecx,%eax), %eax
|
|
ret
|
|
|
|
both of which are inferior to GCC's:
|
|
|
|
_f:
|
|
movl 4(%esp), %edx
|
|
leal 1(%edx), %eax
|
|
addl $2, %edx
|
|
cmpl 8(%esp), %eax
|
|
cmove %edx, %eax
|
|
ret
|
|
_f2:
|
|
movl 4(%esp), %eax
|
|
addl $1, %eax
|
|
xorl %edx, %edx
|
|
cmpl 8(%esp), %eax
|
|
sete %dl
|
|
addl %edx, %eax
|
|
ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
This code:
|
|
|
|
void test(int X) {
|
|
if (X) abort();
|
|
}
|
|
|
|
is currently compiled to:
|
|
|
|
_test:
|
|
subl $12, %esp
|
|
cmpl $0, 16(%esp)
|
|
jne LBB1_1
|
|
addl $12, %esp
|
|
ret
|
|
LBB1_1:
|
|
call L_abort$stub
|
|
|
|
It would be better to produce:
|
|
|
|
_test:
|
|
subl $12, %esp
|
|
cmpl $0, 16(%esp)
|
|
jne L_abort$stub
|
|
addl $12, %esp
|
|
ret
|
|
|
|
This can be applied to any no-return function call that takes no arguments etc.
|
|
Alternatively, the stack save/restore logic could be shrink-wrapped, producing
|
|
something like this:
|
|
|
|
_test:
|
|
cmpl $0, 4(%esp)
|
|
jne LBB1_1
|
|
ret
|
|
LBB1_1:
|
|
subl $12, %esp
|
|
call L_abort$stub
|
|
|
|
Both are useful in different situations. Finally, it could be shrink-wrapped
|
|
and tail called, like this:
|
|
|
|
_test:
|
|
cmpl $0, 4(%esp)
|
|
jne LBB1_1
|
|
ret
|
|
LBB1_1:
|
|
pop %eax # realign stack.
|
|
call L_abort$stub
|
|
|
|
Though this probably isn't worth it.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
We need to teach the codegen to convert two-address INC instructions to LEA
|
|
when the flags are dead (likewise dec). For example, on X86-64, compile:
|
|
|
|
int foo(int A, int B) {
|
|
return A+1;
|
|
}
|
|
|
|
to:
|
|
|
|
_foo:
|
|
leal 1(%edi), %eax
|
|
ret
|
|
|
|
instead of:
|
|
|
|
_foo:
|
|
incl %edi
|
|
movl %edi, %eax
|
|
ret
|
|
|
|
Another example is:
|
|
|
|
;; X's live range extends beyond the shift, so the register allocator
|
|
;; cannot coalesce it with Y. Because of this, a copy needs to be
|
|
;; emitted before the shift to save the register value before it is
|
|
;; clobbered. However, this copy is not needed if the register
|
|
;; allocator turns the shift into an LEA. This also occurs for ADD.
|
|
|
|
; Check that the shift gets turned into an LEA.
|
|
; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -x86-asm-syntax=intel | \
|
|
; RUN: not grep {mov E.X, E.X}
|
|
|
|
%G = external global int
|
|
|
|
int %test1(int %X, int %Y) {
|
|
%Z = add int %X, %Y
|
|
volatile store int %Y, int* %G
|
|
volatile store int %Z, int* %G
|
|
ret int %X
|
|
}
|
|
|
|
int %test2(int %X) {
|
|
%Z = add int %X, 1 ;; inc
|
|
volatile store int %Z, int* %G
|
|
ret int %X
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
This:
|
|
#include <xmmintrin.h>
|
|
unsigned test(float f) {
|
|
return _mm_cvtsi128_si32( (__m128i) _mm_set_ss( f ));
|
|
}
|
|
|
|
Compiles to:
|
|
_test:
|
|
movss 4(%esp), %xmm0
|
|
movd %xmm0, %eax
|
|
ret
|
|
|
|
it should compile to a move from the stack slot directly into eax. DAGCombine
|
|
has this xform, but it is currently disabled until the alignment fields of
|
|
the load/store nodes are trustworthy.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Sometimes it is better to codegen subtractions from a constant (e.g. 7-x) with
|
|
a neg instead of a sub instruction. Consider:
|
|
|
|
int test(char X) { return 7-X; }
|
|
|
|
we currently produce:
|
|
_test:
|
|
movl $7, %eax
|
|
movsbl 4(%esp), %ecx
|
|
subl %ecx, %eax
|
|
ret
|
|
|
|
We would use one fewer register if codegen'd as:
|
|
|
|
movsbl 4(%esp), %eax
|
|
neg %eax
|
|
add $7, %eax
|
|
ret
|
|
|
|
Note that this isn't beneficial if the load can be folded into the sub. In
|
|
this case, we want a sub:
|
|
|
|
int test(int X) { return 7-X; }
|
|
_test:
|
|
movl $7, %eax
|
|
subl 4(%esp), %eax
|
|
ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
For code like:
|
|
phi (undef, x)
|
|
|
|
We get an implicit def on the undef side. If the phi is spilled, we then get:
|
|
implicitdef xmm1
|
|
store xmm1 -> stack
|
|
|
|
It should be possible to teach the x86 backend to "fold" the store into the
|
|
implicitdef, which just deletes the implicit def.
|
|
|
|
These instructions should go away:
|
|
#IMPLICIT_DEF %xmm1
|
|
movaps %xmm1, 192(%esp)
|
|
movaps %xmm1, 224(%esp)
|
|
movaps %xmm1, 176(%esp)
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
This is a "commutable two-address" register coallescing deficiency:
|
|
|
|
define <4 x float> @test1(<4 x float> %V) {
|
|
entry:
|
|
%tmp8 = shufflevector <4 x float> %V, <4 x float> undef,
|
|
<4 x i32> < i32 3, i32 2, i32 1, i32 0 >
|
|
%add = add <4 x float> %tmp8, %V
|
|
ret <4 x float> %add
|
|
}
|
|
|
|
this codegens to:
|
|
|
|
_test1:
|
|
pshufd $27, %xmm0, %xmm1
|
|
addps %xmm0, %xmm1
|
|
movaps %xmm1, %xmm0
|
|
ret
|
|
|
|
instead of:
|
|
|
|
_test1:
|
|
pshufd $27, %xmm0, %xmm1
|
|
addps %xmm1, %xmm0
|
|
ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Leaf functions that require one 4-byte spill slot have a prolog like this:
|
|
|
|
_foo:
|
|
pushl %esi
|
|
subl $4, %esp
|
|
...
|
|
and an epilog like this:
|
|
addl $4, %esp
|
|
popl %esi
|
|
ret
|
|
|
|
It would be smaller, and potentially faster, to push eax on entry and to
|
|
pop into a dummy register instead of using addl/subl of esp. Just don't pop
|
|
into any return registers :)
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
The X86 backend should fold (branch (or (setcc, setcc))) into multiple
|
|
branches. We generate really poor code for:
|
|
|
|
double testf(double a) {
|
|
return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
|
|
}
|
|
|
|
For example, the entry BB is:
|
|
|
|
_testf:
|
|
subl $20, %esp
|
|
pxor %xmm0, %xmm0
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|
movsd 24(%esp), %xmm1
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|
ucomisd %xmm0, %xmm1
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|
setnp %al
|
|
sete %cl
|
|
testb %cl, %al
|
|
jne LBB1_5 # UnifiedReturnBlock
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|
LBB1_1: # cond_true
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|
|
|
|
|
it would be better to replace the last four instructions with:
|
|
|
|
jp LBB1_1
|
|
je LBB1_5
|
|
LBB1_1:
|
|
|
|
We also codegen the inner ?: into a diamond:
|
|
|
|
cvtss2sd LCPI1_0(%rip), %xmm2
|
|
cvtss2sd LCPI1_1(%rip), %xmm3
|
|
ucomisd %xmm1, %xmm0
|
|
ja LBB1_3 # cond_true
|
|
LBB1_2: # cond_true
|
|
movapd %xmm3, %xmm2
|
|
LBB1_3: # cond_true
|
|
movapd %xmm2, %xmm0
|
|
ret
|
|
|
|
We should sink the load into xmm3 into the LBB1_2 block. This should
|
|
be pretty easy, and will nuke all the copies.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
This:
|
|
#include <algorithm>
|
|
inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
|
|
{ return std::make_pair(a + b, a + b < a); }
|
|
bool no_overflow(unsigned a, unsigned b)
|
|
{ return !full_add(a, b).second; }
|
|
|
|
Should compile to:
|
|
|
|
|
|
_Z11no_overflowjj:
|
|
addl %edi, %esi
|
|
setae %al
|
|
ret
|
|
|
|
on x86-64, not:
|
|
|
|
__Z11no_overflowjj:
|
|
addl %edi, %esi
|
|
cmpl %edi, %esi
|
|
setae %al
|
|
movzbl %al, %eax
|
|
ret
|
|
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Re-materialize MOV32r0 etc. with xor instead of changing them to moves if the
|
|
condition register is dead. xor reg reg is shorter than mov reg, #0.
|