llvm/MIR at 17505810d05f9ab6e3110072414ea3a5a349b3f7 - llvm

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-02-24 04:32:09 +00:00

History

Quentin Colombet 17505810d0 [MIRParser] Non-generic virtual register may have a type.

When generic virtual registers get constrained, because of a use on a
target specific operation for instance, we end up with regular virtual
registers with a type and that's perfectly fine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290376 91177308-0d34-0410-b5e6-96231b3b80d8

2016-12-22 21:56:29 +00:00

AArch64

Move .mir tests to appropriate directories

2016-12-09 19:08:15 +00:00

AMDGPU

AMDGPU: Fix handling of 16-bit immediates

2016-12-10 00:39:12 +00:00

ARM

Move test to correct directory

2016-12-17 02:16:26 +00:00

Generic

[MIRPrinter] XFAIL test for powerpc

2016-11-18 20:08:05 +00:00

Hexagon

Move .mir tests to appropriate directories

2016-12-09 19:08:15 +00:00

Mips

MIRParser: Use shorter cfi identifiers

2016-07-26 18:20:00 +00:00

NVPTX

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00

PowerPC

MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

2016-08-24 01:32:41 +00:00

X86

[MIRParser] Non-generic virtual register may have a type.

2016-12-22 21:56:29 +00:00

README

Add README describing the intention of test/CodeGen/MIR

2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.