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8c20158fb0
SystemZTargetLowering::emitStringWrapper() previously loaded the character into R0 before the loop and made R0 live on entry. I'd forgotten that allocatable registers weren't allowed to be live across blocks at this stage, and it confused LiveVariables enough to cause a miscompilation of f3 in memchr-02.ll. This patch instead loads R0 in the loop and leaves LICM to hoist it after RA. This is actually what I'd tried originally, but I went for the manual optimisation after noticing that R0 often wasn't being hoisted. This bug forced me to go back and look at why, now fixed as r188774. We should also try to optimize null checks so that they test the CC result of the SRST directly. The select between null and the SRST GPR result could then usually be deleted as dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188779 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
3.2 KiB
C++
81 lines
3.2 KiB
C++
//===-- SystemZSelectionDAGInfo.h - SystemZ SelectionDAG Info ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the SystemZ subclass for TargetSelectionDAGInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SYSTEMZSELECTIONDAGINFO_H
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#define SYSTEMZSELECTIONDAGINFO_H
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#include "llvm/Target/TargetSelectionDAGInfo.h"
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namespace llvm {
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class SystemZTargetMachine;
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class SystemZSelectionDAGInfo : public TargetSelectionDAGInfo {
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public:
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explicit SystemZSelectionDAGInfo(const SystemZTargetMachine &TM);
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~SystemZSelectionDAGInfo();
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virtual
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SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
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SDValue Dst, SDValue Src,
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SDValue Size, unsigned Align,
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bool IsVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo,
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MachinePointerInfo SrcPtrInfo) const
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LLVM_OVERRIDE;
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virtual SDValue
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EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL,
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SDValue Chain, SDValue Dst, SDValue Byte,
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SDValue Size, unsigned Align, bool IsVolatile,
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MachinePointerInfo DstPtrInfo) const LLVM_OVERRIDE;
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virtual std::pair<SDValue, SDValue>
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EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
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SDValue Src1, SDValue Src2, SDValue Size,
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MachinePointerInfo Op1PtrInfo,
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MachinePointerInfo Op2PtrInfo) const LLVM_OVERRIDE;
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virtual std::pair<SDValue, SDValue>
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EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
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SDValue Src, SDValue Char, SDValue Length,
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MachinePointerInfo SrcPtrInfo) const LLVM_OVERRIDE;
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virtual std::pair<SDValue, SDValue>
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EmitTargetCodeForStrcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
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SDValue Dest, SDValue Src,
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MachinePointerInfo DestPtrInfo,
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MachinePointerInfo SrcPtrInfo,
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bool isStpcpy) const LLVM_OVERRIDE;
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virtual std::pair<SDValue, SDValue>
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EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
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SDValue Src1, SDValue Src2,
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MachinePointerInfo Op1PtrInfo,
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MachinePointerInfo Op2PtrInfo) const LLVM_OVERRIDE;
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virtual std::pair<SDValue, SDValue>
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EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
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SDValue Src, MachinePointerInfo SrcPtrInfo) const
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LLVM_OVERRIDE;
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virtual std::pair<SDValue, SDValue>
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EmitTargetCodeForStrnlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
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SDValue Src, SDValue MaxLength,
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MachinePointerInfo SrcPtrInfo) const LLVM_OVERRIDE;
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};
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}
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#endif
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