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https://github.com/RPCS3/llvm.git
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b3f912b510
r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8
458 lines
10 KiB
LLVM
458 lines
10 KiB
LLVM
; Test sequences that can use RISBG with a zeroed first operand.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test an extraction of bit 0 from a right-shifted value.
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define i32 @f1(i32 %foo) {
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; CHECK-LABEL: f1:
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; CHECK: risbg %r2, %r2, 63, 191, 54
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; CHECK: br %r14
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%shr = lshr i32 %foo, 10
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%and = and i32 %shr, 1
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f2(i64 %foo) {
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; CHECK-LABEL: f2:
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; CHECK: risbg %r2, %r2, 63, 191, 54
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; CHECK: br %r14
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%shr = lshr i64 %foo, 10
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%and = and i64 %shr, 1
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ret i64 %and
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}
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; Test an extraction of other bits from a right-shifted value.
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define i32 @f3(i32 %foo) {
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; CHECK-LABEL: f3:
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; CHECK: risbg %r2, %r2, 60, 189, 42
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; CHECK: br %r14
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%shr = lshr i32 %foo, 22
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%and = and i32 %shr, 12
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f4(i64 %foo) {
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; CHECK-LABEL: f4:
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; CHECK: risbg %r2, %r2, 60, 189, 42
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; CHECK: br %r14
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%shr = lshr i64 %foo, 22
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%and = and i64 %shr, 12
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ret i64 %and
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}
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; Test an extraction of most bits from a right-shifted value.
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; The range should be reduced to exclude the zeroed high bits.
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define i32 @f5(i32 %foo) {
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; CHECK-LABEL: f5:
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; CHECK: risbg %r2, %r2, 34, 188, 62
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; CHECK: br %r14
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%shr = lshr i32 %foo, 2
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%and = and i32 %shr, -8
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f6(i64 %foo) {
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; CHECK-LABEL: f6:
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; CHECK: risbg %r2, %r2, 2, 188, 62
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; CHECK: br %r14
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%shr = lshr i64 %foo, 2
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%and = and i64 %shr, -8
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ret i64 %and
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}
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; Try the next value up (mask ....1111001). This needs a separate shift
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; and mask.
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define i32 @f7(i32 %foo) {
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; CHECK-LABEL: f7:
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; CHECK: srl %r2, 2
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; CHECK: nill %r2, 65529
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; CHECK: br %r14
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%shr = lshr i32 %foo, 2
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%and = and i32 %shr, -7
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f8(i64 %foo) {
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; CHECK-LABEL: f8:
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; CHECK: srlg %r2, %r2, 2
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; CHECK: nill %r2, 65529
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; CHECK: br %r14
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%shr = lshr i64 %foo, 2
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%and = and i64 %shr, -7
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ret i64 %and
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}
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; Test an extraction of bits from a left-shifted value. The range should
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; be reduced to exclude the zeroed low bits.
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define i32 @f9(i32 %foo) {
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; CHECK-LABEL: f9:
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; CHECK: risbg %r2, %r2, 56, 189, 2
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; CHECK: br %r14
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%shr = shl i32 %foo, 2
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%and = and i32 %shr, 255
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f10(i64 %foo) {
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; CHECK-LABEL: f10:
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; CHECK: risbg %r2, %r2, 56, 189, 2
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; CHECK: br %r14
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%shr = shl i64 %foo, 2
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%and = and i64 %shr, 255
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ret i64 %and
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}
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; Try a wrap-around mask (mask ....111100001111). This needs a separate shift
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; and mask.
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define i32 @f11(i32 %foo) {
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; CHECK-LABEL: f11:
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; CHECK: sll %r2, 2
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; CHECK: nill %r2, 65295
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; CHECK: br %r14
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%shr = shl i32 %foo, 2
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%and = and i32 %shr, -241
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f12(i64 %foo) {
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; CHECK-LABEL: f12:
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; CHECK: sllg %r2, %r2, 2
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; CHECK: nill %r2, 65295
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; CHECK: br %r14
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%shr = shl i64 %foo, 2
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%and = and i64 %shr, -241
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ret i64 %and
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}
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; Test an extraction from a rotated value, no mask wraparound.
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; This is equivalent to the lshr case, because the bits from the
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; shl are not used.
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define i32 @f13(i32 %foo) {
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; CHECK-LABEL: f13:
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; CHECK: risbg %r2, %r2, 56, 188, 46
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; CHECK: br %r14
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%parta = shl i32 %foo, 14
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%partb = lshr i32 %foo, 18
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%rotl = or i32 %parta, %partb
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%and = and i32 %rotl, 248
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f14(i64 %foo) {
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; CHECK-LABEL: f14:
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; CHECK: risbg %r2, %r2, 56, 188, 14
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; CHECK: br %r14
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%parta = shl i64 %foo, 14
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%partb = lshr i64 %foo, 50
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%rotl = or i64 %parta, %partb
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%and = and i64 %rotl, 248
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ret i64 %and
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}
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; Try a case in which only the bits from the shl are used.
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define i32 @f15(i32 %foo) {
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; CHECK-LABEL: f15:
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; CHECK: risbg %r2, %r2, 47, 177, 14
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; CHECK: br %r14
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%parta = shl i32 %foo, 14
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%partb = lshr i32 %foo, 18
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%rotl = or i32 %parta, %partb
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%and = and i32 %rotl, 114688
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f16(i64 %foo) {
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; CHECK-LABEL: f16:
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; CHECK: risbg %r2, %r2, 47, 177, 14
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; CHECK: br %r14
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%parta = shl i64 %foo, 14
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%partb = lshr i64 %foo, 50
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%rotl = or i64 %parta, %partb
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%and = and i64 %rotl, 114688
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ret i64 %and
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}
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; Test a 32-bit rotate in which both parts of the OR are needed.
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; This needs a separate shift and mask.
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define i32 @f17(i32 %foo) {
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; CHECK-LABEL: f17:
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; CHECK: rll %r2, %r2, 4
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; CHECK: nilf %r2, 126
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; CHECK: br %r14
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%parta = shl i32 %foo, 4
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%partb = lshr i32 %foo, 28
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%rotl = or i32 %parta, %partb
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%and = and i32 %rotl, 126
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ret i32 %and
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}
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; ...and for i64, where RISBG should do the rotate too.
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define i64 @f18(i64 %foo) {
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; CHECK-LABEL: f18:
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; CHECK: risbg %r2, %r2, 57, 190, 4
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; CHECK: br %r14
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%parta = shl i64 %foo, 4
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%partb = lshr i64 %foo, 60
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%rotl = or i64 %parta, %partb
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%and = and i64 %rotl, 126
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ret i64 %and
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}
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; Test an arithmetic shift right in which some of the sign bits are kept.
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; This needs a separate shift and mask.
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define i32 @f19(i32 %foo) {
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; CHECK-LABEL: f19:
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; CHECK: sra %r2, 28
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; CHECK: nilf %r2, 30
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; CHECK: br %r14
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%shr = ashr i32 %foo, 28
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%and = and i32 %shr, 30
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ret i32 %and
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}
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; ...and again with i64. In this case RISBG is the best way of doing the AND.
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define i64 @f20(i64 %foo) {
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; CHECK-LABEL: f20:
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; CHECK: srag [[REG:%r[0-5]]], %r2, 60
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; CHECK: risbg %r2, [[REG]], 59, 190, 0
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; CHECK: br %r14
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%shr = ashr i64 %foo, 60
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%and = and i64 %shr, 30
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ret i64 %and
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}
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; Now try an arithmetic right shift in which the sign bits aren't needed.
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; Introduce a second use of %shr so that the ashr doesn't decompose to
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; an lshr.
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define i32 @f21(i32 %foo, i32 *%dest) {
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; CHECK-LABEL: f21:
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; CHECK: risbg %r2, %r2, 60, 190, 36
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; CHECK: br %r14
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%shr = ashr i32 %foo, 28
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store i32 %shr, i32 *%dest
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%and = and i32 %shr, 14
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f22(i64 %foo, i64 *%dest) {
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; CHECK-LABEL: f22:
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; CHECK: risbg %r2, %r2, 60, 190, 4
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; CHECK: br %r14
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%shr = ashr i64 %foo, 60
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store i64 %shr, i64 *%dest
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%and = and i64 %shr, 14
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ret i64 %and
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}
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; Check that we use RISBG for shifted values even if the AND is a
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; natural zero extension.
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define i64 @f23(i64 %foo) {
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; CHECK-LABEL: f23:
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; CHECK: risbg %r2, %r2, 56, 191, 62
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; CHECK: br %r14
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%shr = lshr i64 %foo, 2
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%and = and i64 %shr, 255
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ret i64 %and
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}
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; Test a case where the AND comes before a rotate. This needs a separate
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; mask and rotate.
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define i32 @f24(i32 %foo) {
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; CHECK-LABEL: f24:
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; CHECK: nilf %r2, 14
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; CHECK: rll %r2, %r2, 3
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; CHECK: br %r14
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%and = and i32 %foo, 14
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%parta = shl i32 %and, 3
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%partb = lshr i32 %and, 29
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%rotl = or i32 %parta, %partb
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ret i32 %rotl
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}
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; ...and again with i64, where a single RISBG is enough.
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define i64 @f25(i64 %foo) {
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; CHECK-LABEL: f25:
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; CHECK: risbg %r2, %r2, 57, 187, 3
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; CHECK: br %r14
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%and = and i64 %foo, 14
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%parta = shl i64 %and, 3
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%partb = lshr i64 %and, 61
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%rotl = or i64 %parta, %partb
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ret i64 %rotl
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}
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; Test a wrap-around case in which the AND comes before a rotate.
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; This again needs a separate mask and rotate.
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define i32 @f26(i32 %foo) {
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; CHECK-LABEL: f26:
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; CHECK: nill %r2, 65487
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; CHECK: rll %r2, %r2, 5
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; CHECK: br %r14
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%and = and i32 %foo, -49
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%parta = shl i32 %and, 5
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%partb = lshr i32 %and, 27
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%rotl = or i32 %parta, %partb
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ret i32 %rotl
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}
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; ...and again with i64, where a single RISBG is OK.
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define i64 @f27(i64 %foo) {
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; CHECK-LABEL: f27:
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; CHECK: risbg %r2, %r2, 55, 180, 5
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; CHECK: br %r14
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%and = and i64 %foo, -49
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%parta = shl i64 %and, 5
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%partb = lshr i64 %and, 59
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%rotl = or i64 %parta, %partb
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ret i64 %rotl
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}
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; Test a case where the AND comes before a shift left.
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define i32 @f28(i32 %foo) {
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; CHECK-LABEL: f28:
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; CHECK: risbg %r2, %r2, 32, 173, 17
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; CHECK: br %r14
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%and = and i32 %foo, 32766
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%shl = shl i32 %and, 17
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ret i32 %shl
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}
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; ...and again with i64.
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define i64 @f29(i64 %foo) {
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; CHECK-LABEL: f29:
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; CHECK: risbg %r2, %r2, 0, 141, 49
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; CHECK: br %r14
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%and = and i64 %foo, 32766
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%shl = shl i64 %and, 49
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ret i64 %shl
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}
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; Test the next shift up from f28, in which the mask should get shortened.
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define i32 @f30(i32 %foo) {
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; CHECK-LABEL: f30:
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; CHECK: risbg %r2, %r2, 32, 172, 18
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; CHECK: br %r14
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%and = and i32 %foo, 32766
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%shl = shl i32 %and, 18
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ret i32 %shl
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}
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; ...and again with i64.
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define i64 @f31(i64 %foo) {
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; CHECK-LABEL: f31:
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; CHECK: risbg %r2, %r2, 0, 140, 50
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; CHECK: br %r14
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%and = and i64 %foo, 32766
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%shl = shl i64 %and, 50
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ret i64 %shl
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}
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; Test a wrap-around case in which the shift left comes after the AND.
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; We can't use RISBG for the shift in that case.
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define i32 @f32(i32 %foo) {
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; CHECK-LABEL: f32:
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; CHECK: sll %r2
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; CHECK: br %r14
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%and = and i32 %foo, -7
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%shl = shl i32 %and, 10
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ret i32 %shl
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}
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; ...and again with i64.
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define i64 @f33(i64 %foo) {
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; CHECK-LABEL: f33:
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; CHECK: sllg %r2
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; CHECK: br %r14
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%and = and i64 %foo, -7
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%shl = shl i64 %and, 10
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ret i64 %shl
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}
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; Test a case where the AND comes before a shift right.
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define i32 @f34(i32 %foo) {
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; CHECK-LABEL: f34:
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; CHECK: risbg %r2, %r2, 57, 191, 55
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; CHECK: br %r14
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%and = and i32 %foo, 65535
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%shl = lshr i32 %and, 9
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ret i32 %shl
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}
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; ...and again with i64.
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define i64 @f35(i64 %foo) {
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; CHECK-LABEL: f35:
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; CHECK: risbg %r2, %r2, 57, 191, 55
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; CHECK: br %r14
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%and = and i64 %foo, 65535
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%shl = lshr i64 %and, 9
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ret i64 %shl
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}
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; Test a wrap-around case where the AND comes before a shift right.
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; We can't use RISBG for the shift in that case.
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define i32 @f36(i32 %foo) {
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; CHECK-LABEL: f36:
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; CHECK: srl %r2
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; CHECK: br %r14
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%and = and i32 %foo, -25
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%shl = lshr i32 %and, 1
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ret i32 %shl
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}
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; ...and again with i64.
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define i64 @f37(i64 %foo) {
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; CHECK-LABEL: f37:
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; CHECK: srlg %r2
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; CHECK: br %r14
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%and = and i64 %foo, -25
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%shl = lshr i64 %and, 1
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ret i64 %shl
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}
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; Test a combination involving a large ASHR and a shift left. We can't
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; use RISBG there.
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define i64 @f38(i64 %foo) {
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; CHECK-LABEL: f38:
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; CHECK: srag {{%r[0-5]}}
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; CHECK: sllg {{%r[0-5]}}
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; CHECK: br %r14
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%ashr = ashr i64 %foo, 32
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%shl = shl i64 %ashr, 5
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ret i64 %shl
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}
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; Try a similar thing in which no shifted sign bits are kept.
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define i64 @f39(i64 %foo, i64 *%dest) {
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; CHECK-LABEL: f39:
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; CHECK: srag [[REG:%r[01345]]], %r2, 35
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; CHECK: risbg %r2, %r2, 33, 189, 31
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; CHECK: br %r14
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%ashr = ashr i64 %foo, 35
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store i64 %ashr, i64 *%dest
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%shl = shl i64 %ashr, 2
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%and = and i64 %shl, 2147483647
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ret i64 %and
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}
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; ...and again with the next highest shift value, where one sign bit is kept.
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define i64 @f40(i64 %foo, i64 *%dest) {
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; CHECK-LABEL: f40:
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; CHECK: srag [[REG:%r[01345]]], %r2, 36
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; CHECK: risbg %r2, [[REG]], 33, 189, 2
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; CHECK: br %r14
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%ashr = ashr i64 %foo, 36
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store i64 %ashr, i64 *%dest
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%shl = shl i64 %ashr, 2
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%and = and i64 %shl, 2147483647
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ret i64 %and
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}
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