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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
1.2 KiB
LLVM
39 lines
1.2 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
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; Test load/store of global value from global offset table.
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@seed = common global i64 0, align 8
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define void @Initrand() nounwind {
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entry:
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; CHECK: @Initrand
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; CHECK: adrp x[[REG:[0-9]+]], _seed@GOTPAGE
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; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed@GOTPAGEOFF]
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; CHECK: str x{{[0-9]+}}, [x[[REG2]]]
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store i64 74755, i64* @seed, align 8
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ret void
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}
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define i32 @Rand() nounwind {
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entry:
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; CHECK: @Rand
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; CHECK: adrp x[[REG:[0-9]+]], _seed@GOTPAGE
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; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed@GOTPAGEOFF]
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; CHECK: movz x[[REG3:[0-9]+]], #1309
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; CHECK: ldr x[[REG4:[0-9]+]], [x[[REG2]]]
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; CHECK: mul x[[REG5:[0-9]+]], x[[REG4]], x[[REG3]]
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; CHECK: movz x[[REG6:[0-9]+]], #13849
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; CHECK: add x[[REG7:[0-9]+]], x[[REG5]], x[[REG6]]
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; CHECK: orr x[[REG8:[0-9]+]], xzr, #0xffff
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; CHECK: and x[[REG9:[0-9]+]], x[[REG7]], x[[REG8]]
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; CHECK: str x[[REG9]], [x[[REG]]]
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; CHECK: ldr x{{[0-9]+}}, [x[[REG]]]
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%0 = load i64* @seed, align 8
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%mul = mul nsw i64 %0, 1309
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%add = add nsw i64 %mul, 13849
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%and = and i64 %add, 65535
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store i64 %and, i64* @seed, align 8
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%1 = load i64* @seed, align 8
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%conv = trunc i64 %1 to i32
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ret i32 %conv
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}
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