llvm/test/CodeGen/AArch64/hints.ll
Saleem Abdulrasool 01c06d7954 AArch64: add support for llvm.aarch64.hint intrinsic
This adds a llvm.aarch64.hint intrinsic to mirror the llvm.arm.hint in order to
support the various hint intrinsic functions in the ACLE.

Add an optional pattern field that permits the subclass to specify the pattern
that matches the selection.  The intrinsic pattern is set as mayLoad, mayStore,
so overload the value for the definition of the hint instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212883 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-12 21:20:49 +00:00

68 lines
1.1 KiB
LLVM

; RUN: llc -mtriple aarch64-eabi -o - %s | FileCheck %s
declare void @llvm.aarch64.hint(i32) nounwind
define void @hint_nop() {
entry:
tail call void @llvm.aarch64.hint(i32 0) nounwind
ret void
}
; CHECK-LABEL: hint_nop
; CHECK: nop
define void @hint_yield() {
entry:
tail call void @llvm.aarch64.hint(i32 1) nounwind
ret void
}
; CHECK-LABEL: hint_yield
; CHECK: yield
define void @hint_wfe() {
entry:
tail call void @llvm.aarch64.hint(i32 2) nounwind
ret void
}
; CHECK-LABEL: hint_wfe
; CHECK: wfe
define void @hint_wfi() {
entry:
tail call void @llvm.aarch64.hint(i32 3) nounwind
ret void
}
; CHECK-LABEL: hint_wfi
; CHECK: wfi
define void @hint_sev() {
entry:
tail call void @llvm.aarch64.hint(i32 4) nounwind
ret void
}
; CHECK-LABEL: hint_sev
; CHECK: sev
define void @hint_sevl() {
entry:
tail call void @llvm.aarch64.hint(i32 5) nounwind
ret void
}
; CHECK-LABEL: hint_sevl
; CHECK: sevl
define void @hint_undefined() {
entry:
tail call void @llvm.aarch64.hint(i32 8) nounwind
ret void
}
; CHECK-LABEL: hint_undefined
; CHECK: hint #0x8