Zlatko Buljan 279cd1ed0b [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support ... Differential Revision: http://reviews.llvm.org/D18824 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275050 91177308-0d34-0410-b5e6-96231b3b80d8		2016-07-11 07:41:56 +00:00
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invalid-mips2-wrong-error.s	[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support	2016-07-11 07:41:56 +00:00
invalid-mips2.s	[mips] Add support for COP1's Branch-On-Cond-Likely instructions	2014-10-17 14:08:28 +00:00
invalid-mips3-wrong-error.s	[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support	2016-07-11 07:41:56 +00:00
invalid-mips3.s	[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions	2016-06-27 08:23:28 +00:00
invalid-mips4-wrong-error.s	[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support	2016-07-11 07:41:56 +00:00
invalid-mips4.s	[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions	2016-06-27 08:23:28 +00:00
invalid-mips5-wrong-error.s	[mips] Improve the error messages given by MipsAsmParser.	2014-09-16 15:00:52 +00:00
invalid-mips5.s	[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support	2016-07-11 07:41:56 +00:00
invalid-mips32.s	[mips] SYNC $stype instruction was added in Mips32	2014-06-18 17:10:30 +00:00
invalid-mips32r2.s	[mips] Marked the DI/EI instruction aliases as MIPS32r2	2014-10-16 15:23:52 +00:00
valid-xfail.s	[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS.	2014-05-08 15:17:29 +00:00
valid.s	[mips] Weaken asm predicate for memory offsets	2016-05-27 13:56:36 +00:00