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1d003d31da
Encode them directly as an imm argument to G_INTRINSIC*. Since now intrinsics can now define what parameters are required to be immediates, avoid using registers for them. Intrinsics could potentially want a constant that isn't a legal register type. Also, since G_CONSTANT is subject to CSE and legalization, transforms could potentially obscure the value (and create extra work for the selector). The register bank of a G_CONSTANT is also meaningful, so this could throw off future folding and legalization logic for AMDGPU. This will be much more convenient to work with than needing to call getConstantVRegVal and checking if it may have failed for every constant intrinsic parameter. AMDGPU has quite a lot of intrinsics wth immarg operands, many of which need inspection during lowering. Having to find the value in a register is going to add a lot of boilerplate and waste compile time. SelectionDAG has always provided TargetConstant for constants which should not be legalized or materialized in a register. The distinction between Constant and TargetConstant was somewhat fuzzy, and there was no automatic way to force usage of TargetConstant for certain intrinsic parameters. They were both ultimately ConstantSDNode, and it was inconsistently used. It was quite easy to mis-select an instruction requiring an immediate. For SelectionDAG, start emitting TargetConstant for these arguments, and using timm to match them. Most of the work here is to cleanup target handling of constants. Some targets process intrinsics through intermediate custom nodes, which need to preserve TargetConstant usage to match the intrinsic expectation. Pattern inputs now need to distinguish whether a constant is merely compatible with an operand or whether it is mandatory. The GlobalISelEmitter needs to treat timm as a special case of a leaf node, simlar to MachineBasicBlock operands. This should also enable handling of patterns for some G_* instructions with immediates, like G_FENCE or G_EXTRACT. This does include a workaround for a crash in GlobalISelEmitter when ARM tries to uses "imm" in an output with a "timm" pattern source. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372285 91177308-0d34-0410-b5e6-96231b3b80d8
276 lines
13 KiB
C++
276 lines
13 KiB
C++
//===-- SystemZSelectionDAGInfo.cpp - SystemZ SelectionDAG Info -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SystemZSelectionDAGInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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using namespace llvm;
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#define DEBUG_TYPE "systemz-selectiondag-info"
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// Decide whether it is best to use a loop or straight-line code for
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// a block operation of Size bytes with source address Src and destination
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// address Dest. Sequence is the opcode to use for straight-line code
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// (such as MVC) and Loop is the opcode to use for loops (such as MVC_LOOP).
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// Return the chain for the completed operation.
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static SDValue emitMemMem(SelectionDAG &DAG, const SDLoc &DL, unsigned Sequence,
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unsigned Loop, SDValue Chain, SDValue Dst,
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SDValue Src, uint64_t Size) {
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EVT PtrVT = Src.getValueType();
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// The heuristic we use is to prefer loops for anything that would
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// require 7 or more MVCs. With these kinds of sizes there isn't
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// much to choose between straight-line code and looping code,
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// since the time will be dominated by the MVCs themselves.
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// However, the loop has 4 or 5 instructions (depending on whether
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// the base addresses can be proved equal), so there doesn't seem
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// much point using a loop for 5 * 256 bytes or fewer. Anything in
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// the range (5 * 256, 6 * 256) will need another instruction after
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// the loop, so it doesn't seem worth using a loop then either.
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// The next value up, 6 * 256, can be implemented in the same
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// number of straight-line MVCs as 6 * 256 - 1.
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if (Size > 6 * 256)
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return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src,
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DAG.getConstant(Size, DL, PtrVT),
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DAG.getConstant(Size / 256, DL, PtrVT));
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return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src,
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DAG.getConstant(Size, DL, PtrVT));
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}
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SDValue SystemZSelectionDAGInfo::EmitTargetCodeForMemcpy(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
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SDValue Size, unsigned Align, bool IsVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
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if (IsVolatile)
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return SDValue();
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if (auto *CSize = dyn_cast<ConstantSDNode>(Size))
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return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP,
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Chain, Dst, Src, CSize->getZExtValue());
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return SDValue();
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}
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// Handle a memset of 1, 2, 4 or 8 bytes with the operands given by
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// Chain, Dst, ByteVal and Size. These cases are expected to use
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// MVI, MVHHI, MVHI and MVGHI respectively.
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static SDValue memsetStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
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SDValue Dst, uint64_t ByteVal, uint64_t Size,
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unsigned Align, MachinePointerInfo DstPtrInfo) {
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uint64_t StoreVal = ByteVal;
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for (unsigned I = 1; I < Size; ++I)
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StoreVal |= ByteVal << (I * 8);
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return DAG.getStore(
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Chain, DL, DAG.getConstant(StoreVal, DL, MVT::getIntegerVT(Size * 8)),
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Dst, DstPtrInfo, Align);
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}
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SDValue SystemZSelectionDAGInfo::EmitTargetCodeForMemset(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst,
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SDValue Byte, SDValue Size, unsigned Align, bool IsVolatile,
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MachinePointerInfo DstPtrInfo) const {
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EVT PtrVT = Dst.getValueType();
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if (IsVolatile)
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return SDValue();
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if (auto *CSize = dyn_cast<ConstantSDNode>(Size)) {
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uint64_t Bytes = CSize->getZExtValue();
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if (Bytes == 0)
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return SDValue();
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if (auto *CByte = dyn_cast<ConstantSDNode>(Byte)) {
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// Handle cases that can be done using at most two of
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// MVI, MVHI, MVHHI and MVGHI. The latter two can only be
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// used if ByteVal is all zeros or all ones; in other casees,
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// we can move at most 2 halfwords.
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uint64_t ByteVal = CByte->getZExtValue();
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if (ByteVal == 0 || ByteVal == 255 ?
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Bytes <= 16 && countPopulation(Bytes) <= 2 :
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Bytes <= 4) {
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unsigned Size1 = Bytes == 16 ? 8 : 1 << findLastSet(Bytes);
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unsigned Size2 = Bytes - Size1;
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SDValue Chain1 = memsetStore(DAG, DL, Chain, Dst, ByteVal, Size1,
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Align, DstPtrInfo);
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if (Size2 == 0)
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return Chain1;
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Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
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DAG.getConstant(Size1, DL, PtrVT));
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DstPtrInfo = DstPtrInfo.getWithOffset(Size1);
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SDValue Chain2 = memsetStore(DAG, DL, Chain, Dst, ByteVal, Size2,
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std::min(Align, Size1), DstPtrInfo);
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return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
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}
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} else {
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// Handle one and two bytes using STC.
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if (Bytes <= 2) {
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SDValue Chain1 = DAG.getStore(Chain, DL, Byte, Dst, DstPtrInfo, Align);
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if (Bytes == 1)
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return Chain1;
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SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
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DAG.getConstant(1, DL, PtrVT));
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SDValue Chain2 =
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DAG.getStore(Chain, DL, Byte, Dst2, DstPtrInfo.getWithOffset(1),
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/* Alignment = */ 1);
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return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
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}
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}
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assert(Bytes >= 2 && "Should have dealt with 0- and 1-byte cases already");
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// Handle the special case of a memset of 0, which can use XC.
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auto *CByte = dyn_cast<ConstantSDNode>(Byte);
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if (CByte && CByte->getZExtValue() == 0)
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return emitMemMem(DAG, DL, SystemZISD::XC, SystemZISD::XC_LOOP,
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Chain, Dst, Dst, Bytes);
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// Copy the byte to the first location and then use MVC to copy
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// it to the rest.
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Chain = DAG.getStore(Chain, DL, Byte, Dst, DstPtrInfo, Align);
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SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
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DAG.getConstant(1, DL, PtrVT));
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return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP,
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Chain, DstPlus1, Dst, Bytes - 1);
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}
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return SDValue();
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}
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// Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size),
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// deciding whether to use a loop or straight-line code.
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static SDValue emitCLC(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
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SDValue Src1, SDValue Src2, uint64_t Size) {
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SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
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EVT PtrVT = Src1.getValueType();
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// A two-CLC sequence is a clear win over a loop, not least because it
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// needs only one branch. A three-CLC sequence needs the same number
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// of branches as a loop (i.e. 2), but is shorter. That brings us to
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// lengths greater than 768 bytes. It seems relatively likely that
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// a difference will be found within the first 768 bytes, so we just
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// optimize for the smallest number of branch instructions, in order
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// to avoid polluting the prediction buffer too much. A loop only ever
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// needs 2 branches, whereas a straight-line sequence would need 3 or more.
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if (Size > 3 * 256)
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return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
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DAG.getConstant(Size, DL, PtrVT),
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DAG.getConstant(Size / 256, DL, PtrVT));
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return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
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DAG.getConstant(Size, DL, PtrVT));
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}
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// Convert the current CC value into an integer that is 0 if CC == 0,
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// greater than zero if CC == 1 and less than zero if CC >= 2.
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// The sequence starts with IPM, which puts CC into bits 29 and 28
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// of an integer and clears bits 30 and 31.
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static SDValue addIPMSequence(const SDLoc &DL, SDValue CCReg,
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SelectionDAG &DAG) {
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SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, CCReg);
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SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM,
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DAG.getConstant(30 - SystemZ::IPM_CC, DL, MVT::i32));
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SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL,
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DAG.getConstant(30, DL, MVT::i32));
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return SRA;
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}
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std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::EmitTargetCodeForMemcmp(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
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SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo,
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MachinePointerInfo Op2PtrInfo) const {
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if (auto *CSize = dyn_cast<ConstantSDNode>(Size)) {
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uint64_t Bytes = CSize->getZExtValue();
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assert(Bytes > 0 && "Caller should have handled 0-size case");
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// Swap operands to invert CC == 1 vs. CC == 2 cases.
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SDValue CCReg = emitCLC(DAG, DL, Chain, Src2, Src1, Bytes);
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Chain = CCReg.getValue(1);
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return std::make_pair(addIPMSequence(DL, CCReg, DAG), Chain);
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}
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return std::make_pair(SDValue(), SDValue());
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}
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std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src,
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SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const {
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// Use SRST to find the character. End is its address on success.
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EVT PtrVT = Src.getValueType();
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SDVTList VTs = DAG.getVTList(PtrVT, MVT::i32, MVT::Other);
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Length = DAG.getZExtOrTrunc(Length, DL, PtrVT);
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Char = DAG.getZExtOrTrunc(Char, DL, MVT::i32);
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Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char,
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DAG.getConstant(255, DL, MVT::i32));
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SDValue Limit = DAG.getNode(ISD::ADD, DL, PtrVT, Src, Length);
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SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain,
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Limit, Src, Char);
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SDValue CCReg = End.getValue(1);
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Chain = End.getValue(2);
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// Now select between End and null, depending on whether the character
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// was found.
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SDValue Ops[] = {
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End, DAG.getConstant(0, DL, PtrVT),
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DAG.getTargetConstant(SystemZ::CCMASK_SRST, DL, MVT::i32),
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DAG.getTargetConstant(SystemZ::CCMASK_SRST_FOUND, DL, MVT::i32), CCReg};
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End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, PtrVT, Ops);
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return std::make_pair(End, Chain);
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}
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std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dest,
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SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo,
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bool isStpcpy) const {
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SDVTList VTs = DAG.getVTList(Dest.getValueType(), MVT::Other);
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SDValue EndDest = DAG.getNode(SystemZISD::STPCPY, DL, VTs, Chain, Dest, Src,
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DAG.getConstant(0, DL, MVT::i32));
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return std::make_pair(isStpcpy ? EndDest : Dest, EndDest.getValue(1));
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}
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std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
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SDValue Src2, MachinePointerInfo Op1PtrInfo,
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MachinePointerInfo Op2PtrInfo) const {
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SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::i32, MVT::Other);
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// Swap operands to invert CC == 1 vs. CC == 2 cases.
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SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1,
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DAG.getConstant(0, DL, MVT::i32));
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SDValue CCReg = Unused.getValue(1);
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Chain = Unused.getValue(2);
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return std::make_pair(addIPMSequence(DL, CCReg, DAG), Chain);
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}
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// Search from Src for a null character, stopping once Src reaches Limit.
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// Return a pair of values, the first being the number of nonnull characters
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// and the second being the out chain.
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//
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// This can be used for strlen by setting Limit to 0.
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static std::pair<SDValue, SDValue> getBoundedStrlen(SelectionDAG &DAG,
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const SDLoc &DL,
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SDValue Chain, SDValue Src,
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SDValue Limit) {
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EVT PtrVT = Src.getValueType();
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SDVTList VTs = DAG.getVTList(PtrVT, MVT::i32, MVT::Other);
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SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain,
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Limit, Src, DAG.getConstant(0, DL, MVT::i32));
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Chain = End.getValue(2);
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SDValue Len = DAG.getNode(ISD::SUB, DL, PtrVT, End, Src);
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return std::make_pair(Len, Chain);
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}
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std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src,
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MachinePointerInfo SrcPtrInfo) const {
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EVT PtrVT = Src.getValueType();
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return getBoundedStrlen(DAG, DL, Chain, Src, DAG.getConstant(0, DL, PtrVT));
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}
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std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(
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SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src,
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SDValue MaxLength, MachinePointerInfo SrcPtrInfo) const {
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EVT PtrVT = Src.getValueType();
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MaxLength = DAG.getZExtOrTrunc(MaxLength, DL, PtrVT);
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SDValue Limit = DAG.getNode(ISD::ADD, DL, PtrVT, Src, MaxLength);
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return getBoundedStrlen(DAG, DL, Chain, Src, Limit);
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}
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