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https://github.com/RPCS3/llvm.git
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1c3af779fc
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
1.1 KiB
LLVM
56 lines
1.1 KiB
LLVM
; RUN: llc -march=thumb -mattr=+thumb2 < %s | FileCheck %s
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; 171 = 0x000000ab
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define i64 @f1(i64 %a) {
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; CHECK: f1
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; CHECK: subs r0, #171
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; CHECK: sbc r1, r1, #0
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%tmp = sub i64 %a, 171
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ret i64 %tmp
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}
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; 1179666 = 0x00120012
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define i64 @f2(i64 %a) {
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; CHECK: f2
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; CHECK: subs.w r0, r0, #1179666
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; CHECK: sbc r1, r1, #0
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%tmp = sub i64 %a, 1179666
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ret i64 %tmp
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}
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; 872428544 = 0x34003400
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define i64 @f3(i64 %a) {
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; CHECK: f3
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; CHECK: subs.w r0, r0, #872428544
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; CHECK: sbc r1, r1, #0
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%tmp = sub i64 %a, 872428544
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ret i64 %tmp
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}
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; 1448498774 = 0x56565656
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define i64 @f4(i64 %a) {
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; CHECK: f4
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; CHECK: subs.w r0, r0, #1448498774
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; CHECK: sbc r1, r1, #0
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%tmp = sub i64 %a, 1448498774
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ret i64 %tmp
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}
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; 66846720 = 0x03fc0000
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define i64 @f5(i64 %a) {
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; CHECK: f5
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; CHECK: subs.w r0, r0, #66846720
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; CHECK: sbc r1, r1, #0
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%tmp = sub i64 %a, 66846720
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ret i64 %tmp
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}
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; 734439407618 = 0x000000ab00000002
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define i64 @f6(i64 %a) {
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; CHECK: f6
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; CHECK: subs r0, #2
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; CHECK: sbc r1, r1, #171
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%tmp = sub i64 %a, 734439407618
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ret i64 %tmp
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}
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