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eb7876083d
This instructions writes to an 32-bit SGPR. This change required adding the 32-bit VCC_LO and VCC_HI registers, because the full VCC register is 64 bits. This fixes verifier errors on several of the indirect addressing piglit tests. Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204055 91177308-0d34-0410-b5e6-96231b3b80d8
326 lines
11 KiB
C++
326 lines
11 KiB
C++
//===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// The AMDGPUAsmPrinter is used to print both assembly string and also binary
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/// code. When passed an MCAsmStreamer it prints assembly and when passed
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/// an MCObjectStreamer it outputs binary code.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPUAsmPrinter.h"
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#include "AMDGPU.h"
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#include "R600Defines.h"
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#include "R600MachineFunctionInfo.h"
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#include "R600RegisterInfo.h"
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#include "SIDefines.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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using namespace llvm;
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static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
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MCStreamer &Streamer) {
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return new AMDGPUAsmPrinter(tm, Streamer);
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}
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extern "C" void LLVMInitializeR600AsmPrinter() {
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TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
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}
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AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer) {
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DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
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}
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bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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SetupMachineFunction(MF);
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OutStreamer.emitRawComment(Twine('@') + MF.getName() + Twine(':'));
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MCContext &Context = getObjFileLowering().getContext();
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const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
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ELF::SHT_PROGBITS, 0,
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SectionKind::getReadOnly());
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OutStreamer.SwitchSection(ConfigSection);
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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SIProgramInfo KernelInfo;
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if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
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findNumUsedRegistersSI(MF, KernelInfo.NumSGPR, KernelInfo.NumVGPR);
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EmitProgramInfoSI(MF, KernelInfo);
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} else {
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EmitProgramInfoR600(MF);
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}
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DisasmLines.clear();
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HexLines.clear();
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DisasmLineMaxLen = 0;
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OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
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EmitFunctionBody();
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if (isVerbose()) {
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const MCSectionELF *CommentSection
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= Context.getELFSection(".AMDGPU.csdata",
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ELF::SHT_PROGBITS, 0,
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SectionKind::getReadOnly());
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OutStreamer.SwitchSection(CommentSection);
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if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
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OutStreamer.emitRawComment(" Kernel info:", false);
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OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
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false);
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OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
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false);
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} else {
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R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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OutStreamer.emitRawComment(
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Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
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}
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}
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if (STM.dumpCode()) {
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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MF.dump();
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#endif
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if (DisasmEnabled) {
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OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
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ELF::SHT_NOTE, 0,
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SectionKind::getReadOnly()));
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for (size_t i = 0; i < DisasmLines.size(); ++i) {
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std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
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Comment += " ; " + HexLines[i] + "\n";
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OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
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OutStreamer.EmitBytes(StringRef(Comment));
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}
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}
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}
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return false;
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}
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void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
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unsigned MaxGPR = 0;
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bool killPixel = false;
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const R600RegisterInfo * RI =
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static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
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R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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if (MI.getOpcode() == AMDGPU::KILLGT)
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killPixel = true;
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unsigned numOperands = MI.getNumOperands();
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for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
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MachineOperand & MO = MI.getOperand(op_idx);
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if (!MO.isReg())
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continue;
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unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
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// Register with value > 127 aren't GPR
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if (HWReg > 127)
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continue;
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MaxGPR = std::max(MaxGPR, HWReg);
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}
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}
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}
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unsigned RsrcReg;
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if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
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// Evergreen / Northern Islands
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switch (MFI->ShaderType) {
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default: // Fall through
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case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
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case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
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case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
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case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
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}
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} else {
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// R600 / R700
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switch (MFI->ShaderType) {
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default: // Fall through
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case ShaderType::GEOMETRY: // Fall through
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case ShaderType::COMPUTE: // Fall through
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case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
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case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
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}
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}
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OutStreamer.EmitIntValue(RsrcReg, 4);
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OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
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S_STACK_SIZE(MFI->StackSize), 4);
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OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
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OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
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if (MFI->ShaderType == ShaderType::COMPUTE) {
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OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
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OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
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}
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}
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void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF,
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unsigned &NumSGPR,
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unsigned &NumVGPR) const {
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unsigned MaxSGPR = 0;
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unsigned MaxVGPR = 0;
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bool VCCUsed = false;
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const SIRegisterInfo * RI =
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static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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unsigned numOperands = MI.getNumOperands();
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for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
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MachineOperand &MO = MI.getOperand(op_idx);
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unsigned width = 0;
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bool isSGPR = false;
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if (!MO.isReg()) {
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continue;
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}
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unsigned reg = MO.getReg();
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if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
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reg == AMDGPU::VCC_HI) {
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VCCUsed = true;
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continue;
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}
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switch (reg) {
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default: break;
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case AMDGPU::SCC:
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case AMDGPU::EXEC:
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case AMDGPU::M0:
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continue;
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}
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if (AMDGPU::SReg_32RegClass.contains(reg)) {
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isSGPR = true;
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width = 1;
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} else if (AMDGPU::VReg_32RegClass.contains(reg)) {
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isSGPR = false;
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width = 1;
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} else if (AMDGPU::SReg_64RegClass.contains(reg)) {
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isSGPR = true;
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width = 2;
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} else if (AMDGPU::VReg_64RegClass.contains(reg)) {
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isSGPR = false;
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width = 2;
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} else if (AMDGPU::VReg_96RegClass.contains(reg)) {
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isSGPR = false;
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width = 3;
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} else if (AMDGPU::SReg_128RegClass.contains(reg)) {
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isSGPR = true;
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width = 4;
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} else if (AMDGPU::VReg_128RegClass.contains(reg)) {
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isSGPR = false;
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width = 4;
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} else if (AMDGPU::SReg_256RegClass.contains(reg)) {
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isSGPR = true;
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width = 8;
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} else if (AMDGPU::VReg_256RegClass.contains(reg)) {
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isSGPR = false;
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width = 8;
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} else if (AMDGPU::SReg_512RegClass.contains(reg)) {
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isSGPR = true;
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width = 16;
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} else if (AMDGPU::VReg_512RegClass.contains(reg)) {
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isSGPR = false;
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width = 16;
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} else {
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llvm_unreachable("Unknown register class");
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}
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unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
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unsigned maxUsed = hwReg + width - 1;
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if (isSGPR) {
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MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
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} else {
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MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
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}
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}
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}
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}
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if (VCCUsed)
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MaxSGPR += 2;
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NumSGPR = MaxSGPR;
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NumVGPR = MaxVGPR;
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}
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void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &Out,
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MachineFunction &MF) const {
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findNumUsedRegistersSI(MF, Out.NumSGPR, Out.NumVGPR);
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}
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void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
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const SIProgramInfo &KernelInfo) {
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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unsigned RsrcReg;
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switch (MFI->ShaderType) {
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default: // Fall through
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case ShaderType::COMPUTE: RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
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case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
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case ShaderType::PIXEL: RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
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case ShaderType::VERTEX: RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
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}
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OutStreamer.EmitIntValue(RsrcReg, 4);
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OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
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S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
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unsigned LDSAlignShift;
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if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
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// LDS is allocated in 64 dword blocks
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LDSAlignShift = 8;
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} else {
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// LDS is allocated in 128 dword blocks
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LDSAlignShift = 9;
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}
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unsigned LDSBlocks =
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RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
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if (MFI->ShaderType == ShaderType::COMPUTE) {
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OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
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OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(LDSBlocks), 4);
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}
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if (MFI->ShaderType == ShaderType::PIXEL) {
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OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
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OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
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OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
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OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
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}
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}
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