mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-26 14:15:53 +00:00
aa6ec15caf
SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions.
v2:
- Fix encoding of Lane Mask
- Use correct register flags, so we don't overwrite the low dword
when restoring multi-dword registers.
v3:
- Register spilling seems to hang the GPU, so replace all shaders
that need spilling with a dummy shader.
v4:
- Fix *LANE definitions
- Change destination reg class for 32-bit SMRD instructions
v5:
- Remove small optimization that was crashing Serious Sam 3.
https://bugs.freedesktop.org/show_bug.cgi?id=68224
https://bugs.freedesktop.org/show_bug.cgi?id=71285
NOTE: This is a candidate for the 3.4 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195880 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
1.7 KiB
C++
63 lines
1.7 KiB
C++
//===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
#ifndef SIMACHINEFUNCTIONINFO_H_
|
|
#define SIMACHINEFUNCTIONINFO_H_
|
|
|
|
#include "AMDGPUMachineFunction.h"
|
|
#include <map>
|
|
|
|
namespace llvm {
|
|
|
|
class MachineRegisterInfo;
|
|
|
|
/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
|
|
/// tells the hardware which interpolation parameters to load.
|
|
class SIMachineFunctionInfo : public AMDGPUMachineFunction {
|
|
virtual void anchor();
|
|
public:
|
|
|
|
struct SpilledReg {
|
|
unsigned VGPR;
|
|
int Lane;
|
|
SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
|
|
SpilledReg() : VGPR(0), Lane(-1) { }
|
|
bool hasLane() { return Lane != -1;}
|
|
};
|
|
|
|
struct RegSpillTracker {
|
|
private:
|
|
unsigned CurrentLane;
|
|
std::map<unsigned, SpilledReg> SpilledRegisters;
|
|
public:
|
|
unsigned LaneVGPR;
|
|
RegSpillTracker() : CurrentLane(0), SpilledRegisters(), LaneVGPR(0) { }
|
|
unsigned getNextLane(MachineRegisterInfo &MRI);
|
|
void addSpilledReg(unsigned FrameIndex, unsigned Reg, int Lane = -1);
|
|
const SpilledReg& getSpilledReg(unsigned FrameIndex);
|
|
bool programSpillsRegisters() { return !SpilledRegisters.empty(); }
|
|
};
|
|
|
|
// SIMachineFunctionInfo definition
|
|
|
|
SIMachineFunctionInfo(const MachineFunction &MF);
|
|
unsigned PSInputAddr;
|
|
struct RegSpillTracker SpillTracker;
|
|
};
|
|
|
|
} // End namespace llvm
|
|
|
|
|
|
#endif //_SIMACHINEFUNCTIONINFO_H_
|