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2684ddd72e
Ideally only those transform passes that run at -O0 remain enabled, in reality we get as close as we reasonably can. Passes are responsible for disabling themselves, it's not the job of the pass manager to do it for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200892 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
3.2 KiB
LLVM
75 lines
3.2 KiB
LLVM
; RUN: opt -S -debug %s 2>&1 | FileCheck %s --check-prefix=OPT-O0
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; RUN: opt -O1 -S -debug %s 2>&1 | FileCheck %s --check-prefix=OPT-O1
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; RUN: opt -O2 -S -debug %s 2>&1 | FileCheck %s --check-prefix=OPT-O1 --check-prefix=OPT-O2O3
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; RUN: opt -O3 -S -debug %s 2>&1 | FileCheck %s --check-prefix=OPT-O1 --check-prefix=OPT-O2O3
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; RUN: opt -bb-vectorize -dce -die -loweratomic -S -debug %s 2>&1 | FileCheck %s --check-prefix=OPT-MORE
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; RUN: opt -indvars -licm -loop-deletion -loop-extract -loop-idiom -loop-instsimplify -loop-reduce -loop-reroll -loop-rotate -loop-unroll -loop-unswitch -S -debug %s 2>&1 | FileCheck %s --check-prefix=OPT-LOOP
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; REQUIRES: asserts
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; This test verifies that we don't run target independent IR-level
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; optimizations on optnone functions.
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; Function Attrs: noinline optnone
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define i32 @_Z3fooi(i32 %x) #0 {
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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br label %while.cond
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while.cond: ; preds = %while.body, %entry
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%0 = load i32* %x.addr, align 4
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%dec = add nsw i32 %0, -1
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store i32 %dec, i32* %x.addr, align 4
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%tobool = icmp ne i32 %0, 0
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br i1 %tobool, label %while.body, label %while.end
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while.body: ; preds = %while.cond
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br label %while.cond
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while.end: ; preds = %while.cond
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ret i32 0
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}
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attributes #0 = { optnone noinline }
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; Nothing that runs at -O0 gets skipped.
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; OPT-O0-NOT: Skipping pass
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; IR passes run at -O1 and higher.
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; OPT-O1-DAG: Skipping pass 'Aggressive Dead Code Elimination'
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; OPT-O1-DAG: Skipping pass 'Combine redundant instructions'
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; OPT-O1-DAG: Skipping pass 'Dead Store Elimination'
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; OPT-O1-DAG: Skipping pass 'Early CSE'
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; OPT-O1-DAG: Skipping pass 'Jump Threading'
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; OPT-O1-DAG: Skipping pass 'MemCpy Optimization'
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; OPT-O1-DAG: Skipping pass 'Reassociate expressions'
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; OPT-O1-DAG: Skipping pass 'Simplify the CFG'
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; OPT-O1-DAG: Skipping pass 'Sparse Conditional Constant Propagation'
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; OPT-O1-DAG: Skipping pass 'SROA'
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; OPT-O1-DAG: Skipping pass 'Tail Call Elimination'
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; OPT-O1-DAG: Skipping pass 'Value Propagation'
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; Additional IR passes run at -O2 and higher.
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; OPT-O2O3-DAG: Skipping pass 'Global Value Numbering'
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; OPT-O2O3-DAG: Skipping pass 'SLP Vectorizer'
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; Additional IR passes that opt doesn't turn on by default.
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; OPT-MORE-DAG: Skipping pass 'Basic-Block Vectorization'
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; OPT-MORE-DAG: Skipping pass 'Dead Code Elimination'
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; OPT-MORE-DAG: Skipping pass 'Dead Instruction Elimination'
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; OPT-MORE-DAG: Skipping pass 'Lower atomic intrinsics
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; Loop IR passes that opt doesn't turn on by default.
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; OPT-LOOP-DAG: Skipping pass 'Delete dead loops'
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; OPT-LOOP-DAG: Skipping pass 'Extract loops into new functions'
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; OPT-LOOP-DAG: Skipping pass 'Induction Variable Simplification'
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; OPT-LOOP-DAG: Skipping pass 'Loop Invariant Code Motion'
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; OPT-LOOP-DAG: Skipping pass 'Loop Strength Reduction'
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; OPT-LOOP-DAG: Skipping pass 'Recognize loop idioms'
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; OPT-LOOP-DAG: Skipping pass 'Reroll loops'
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; OPT-LOOP-DAG: Skipping pass 'Rotate Loops'
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; OPT-LOOP-DAG: Skipping pass 'Simplify instructions in loops'
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; OPT-LOOP-DAG: Skipping pass 'Unroll loops'
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; OPT-LOOP-DAG: Skipping pass 'Unswitch loops'
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