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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
3.6 KiB
LLVM
104 lines
3.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; The code generated by sdiv is long and complex and may frequently change.
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; The goal of this test is to make sure the ISel doesn't fail.
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;
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; This program was previously failing to compile when one of the selectcc
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; opcodes generated by the sdiv lowering was being legalized and optimized to:
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; selectcc Remainder -1, 0, -1, SETGT
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; This was fixed by adding an additional pattern in R600Instructions.td to
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; match this pattern with a CNDGE_INT.
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; FUNC-LABEL: {{^}}sdiv_i32:
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; EG: CF_END
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define void @sdiv_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in
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%den = load i32 addrspace(1) * %den_ptr
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%result = sdiv i32 %num, %den
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}sdiv_i32_4:
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define void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%num = load i32 addrspace(1) * %in
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%result = sdiv i32 %num, 4
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; Multiply by a weird constant to make sure setIntDivIsCheap is
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; working.
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; FUNC-LABEL: {{^}}slow_sdiv_i32_3435:
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; SI: buffer_load_dword [[VAL:v[0-9]+]],
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; SI: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x98a1930b
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; SI: v_mul_hi_i32 [[TMP:v[0-9]+]], [[VAL]], [[MAGIC]]
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; SI: v_add_i32
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; SI: v_lshrrev_b32
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; SI: v_ashrrev_i32
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; SI: v_add_i32
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; SI: buffer_store_dword
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; SI: s_endpgm
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define void @slow_sdiv_i32_3435(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%num = load i32 addrspace(1) * %in
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%result = sdiv i32 %num, 3435
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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define void @sdiv_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%den_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%num = load <2 x i32> addrspace(1) * %in
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%den = load <2 x i32> addrspace(1) * %den_ptr
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%result = sdiv <2 x i32> %num, %den
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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define void @sdiv_v2i32_4(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%num = load <2 x i32> addrspace(1) * %in
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%result = sdiv <2 x i32> %num, <i32 4, i32 4>
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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define void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%den_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%num = load <4 x i32> addrspace(1) * %in
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%den = load <4 x i32> addrspace(1) * %den_ptr
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%result = sdiv <4 x i32> %num, %den
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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define void @sdiv_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%num = load <4 x i32> addrspace(1) * %in
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%result = sdiv <4 x i32> %num, <i32 4, i32 4, i32 4, i32 4>
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; Tests for 64-bit divide bypass.
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; define void @test_get_quotient(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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; %result = sdiv i64 %a, %b
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; store i64 %result, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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; define void @test_get_remainder(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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; %result = srem i64 %a, %b
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; store i64 %result, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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; define void @test_get_quotient_and_remainder(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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; %resultdiv = sdiv i64 %a, %b
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; %resultrem = srem i64 %a, %b
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; %result = add i64 %resultdiv, %resultrem
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; store i64 %result, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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