JF Bastien 1fe907e7f2 ARM FastISel fix load register classes
The register classes when emitting loads weren't quite restricting enough, leading to MI verification failure on the result register.

These are new failures that weren't there the first time I tried enabling ARM FastISel for new targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 00:20:24 +00:00
..
2013-06-07 18:35:53 +00:00